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Visitor tuohyci
Registered: ‎05-26-2014

Interfacing custom ip with AXI DMA



So I'm a relative beginner looking to build a hardware accelerator module for the Zynq platform. This module will need to take in and process a large quantity of data, it is my understanding that for such an application using an AXI DMA engine is suitable. I have been trying to develop a simple module in the form of a FIFO in order to test communication with the AXIS standard. My system synthesises generates a bit stream fine but the test program I have written does no work when I attempt to run it. The same code works fine for a hardware design the replaces my custom module with the AXI Stream Data FIFO IP block. To be specific the code attempts to copy an array from one address to another, using my hardware design only a single value appears to be copied.


I have a test bench to test the setting of the VALID ad READY signals  and I am unsure if they are the issue or if there is another aspect to the signaling that the DMA controller needs and I am not addressing. I have attached the VHDL code and test bench. One thing I have been attempting is to try run an identical simulation of the standard AXI Stream Data FIFO IP block to see how it's signal responses differ from my own but I have as of yet been unable to figure out if this is possible. Any help you could provide woud be great

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