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Observer alexafi
Observer
8,070 Views
Registered: ‎11-13-2012

Is ACP using the cache on Zynq?

Hi all,

 

in my last post http://forums.xilinx.com/t5/Embedded-Processors-and/Accessing-DDR-from-PL-on-Zynq/td-p/322173

I figured out how to connect my accelerator to the HP slave port of the PS.

 

I am also able to communicate to the ACP port, which I expected to produce better results, since it can use the caches, but it didn't, it was much slower.

 

My question is:

With ACP, after a cache miss, will the data end up in cache? In other words, can the accelerator connected to ACP benefit from the PS' memory hierarchy as if it's the third core?

 

If yes, what signals should be set to achieve this? I know that a read is coherent when ARUSER[0] = 1 and ARCACHE[1] = 1. I tried all combinations of user bits for a shareable device described here with no luck. http://infocenter.arm.com/help/topic/com.arm.doc.ddi0434b/CACIECEG.html

 

Thanks,

Alex

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6 Replies
Contributor
Contributor
7,723 Views
Registered: ‎01-24-2013

Re: Is ACP using the cache on Zynq?

I'm having a similar problem.  I've connected my peripheral (which is just a counter) to the ACP via a central DMA engine.  I can DMA to and from the peripheral, but I have to invalidate the cache to see the values I read, just as if I was using the HP port directly to DRAM.  In my case, using ACP is the same speed as using the HP port.

 

My understanding was that I could just reconnect the bus to the ACP instead of an HP slave port, and cache coherence would be handled automatically.  Is that true?  Are there other settings or configuration things I need to do?

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Xilinx Employee
Xilinx Employee
7,709 Views
Registered: ‎02-01-2008

Re: Is ACP using the cache on Zynq?

alex: I usually tie high all acp AxCACHE and AxUSER signals. You only mentioned ARCACHE and ARUSER. Did you also tie off AWCACHE and AWUSER?

 

Steven: The easiest way to enable coherency for all accesses on ACP port is to enable the tie off AxUSER option that exists in the same place as where you enable the ACP port in the processing system IP customization. There is a simular option in XPS.

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Contributor
Contributor
7,700 Views
Registered: ‎01-24-2013

Re: Is ACP using the cache on Zynq?

John - Where is this option in XPS?

In the ACP configuration pane, I see the option "Use slave driven AxUSER values" (C_USE_DEFAULT_ACP_USER_VAL), which I left unchecked, per this thread.  However, the descriptions seem contradictory - I would assume "slave driven" is the opposite of "DEFAULT_ACP_USER_VAL"?


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Contributor
Contributor
7,686 Views
Registered: ‎01-24-2013

Re: Is ACP using the cache on Zynq?

Checking the "Use slave driven AxUSER values"  box does in fact work.  Checking the box sets the parameter C_USE_DEFAULT_ACP_USER_VAL to 1, which I assume sets the peripheral to use the default values and always enforce coherency.

 

It would really help if the C_USE_DEFAULT_ACP_USER_VAL parameter were documented!  I couldn't find any reference to it in the ps7 datasheet (ds871), or on Google, for that matter.

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Visitor andreforme
Visitor
5,846 Views
Registered: ‎03-04-2015

Re: Is ACP using the cache on Zynq?

I had the same problem. I had to write some data from a custom IP to OCM through ACP port. Initially data wasn’t cache coherent. I solved the problem changing the memory attributes of the used OCM section in the translation table (using Xil_SetTlbAttributes function). Setting the Shareable bit (S) to 1 solve the problem.

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Contributor
Contributor
2,180 Views
Registered: ‎02-24-2018

Re: Is ACP using the cache on Zynq?

Hi alex,

 

Recently I also notice that in some case, the ACP and the HP port have the almost same speed.I think the cache doesn't work.Do you have some ideas about that now?

 

Regards

Crystal

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