Is TVALID timing different in Data Mover and 10G Ethernet MAC?

[uyeshiro]

Hello.

I have an AXI Datamover mm2s stream output going from the Datamover through a AXIS Data FIFO to an AXI 10G Ethernet core transmit input.  The Datamover spec shows the mm2s tvalid signal asserting on the clock before the first data is valid (figure 2-8).  The 10G spec shows transmit tvalid asserting in the same clock period where the first data is valid (figure 3-9).  When I run this on our board, the far end of the 10G transmit receives a packet with a clock's worth of junk data prepended to the packet, which trashes the packet.  Looking at the mm2s/transmit channel with the ILA, this extra clock's worth of data is accepted by the 10G transmit because tvalid asserts one clock before the real data is valid, as the Datamover spec specifies.  This is propagated through the AXIS Data FIFO.

What am I missing here?  I don't understand how this can work as is.

Any help would be appreciated.

[uyeshiro · Accepted solution]

This seems to be pilot error, though the documentation is still misleading.

The dual port memories from which the Data Mover was reading had a primitive output register set.  Things worked when this was unchecked.  I also made sure there were no debug connections to the port.