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Visitor enriqeat2
Visitor
369 Views
Registered: ‎01-22-2019

Is an AXI4 Lite peripheral a Soft or Hard IP? and how many input clocks should it have?

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1. I created an AXI4 Lite peripheral, how do I know if this is a soft or hard IP? 

2. The IP block that I created for Zynq performs actions from processes that are synchronized with the 125 Mhz clock of the PL. Now, I see that my AXI IP has another clock input from from the PS, and this could be modified. I want everything on the PL to work with a 125Mhz clock since, it is what´s been designed, but I want to know if I coud have both clocks on the input of the IP, or if I only should have one. does the clock from the PS has anything to do with the internal PL clock for the processes or does it only affect transactions for the Axi communications?. By the way, the whole aplication works when I send comands from SDK.

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Moderator
Moderator
294 Views
Registered: ‎11-09-2015

Re: Is an AXI4 Lite peripheral a Soft or Hard IP? and how many input clocks should it have?

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@enriqeat2 wrote:

 

1. I created an AXI4 Lite peripheral, how do I know if this is a soft or hard IP?

[Florent] "I created" -> this is a soft IP

A hard IP is to call an IP which is physically on the silicon. Ex. the Zynq processor.

Even if you do not have it in your vivado design, it will always be in the device

2. The IP block that I created for Zynq performs actions from processes that are synchronized with the 125 Mhz clock of the PL. Now, I see that my AXI IP has another clock input from from the PS, and this could be modified. I want everything on the PL to work with a 125Mhz clock since, it is what´s been designed, but I want to know if I coud have both clocks on the input of the IP, or if I only should have one. does the clock from the PS has anything to do with the internal PL clock for the processes or does it only affect transactions for the Axi communications?. By the way, the whole aplication works when I send comands from SDK.


[Florent] - You can only have one clock input if you need only one. You will need to connect the AXI interconnect with M00_ACLK connected to your clock clk and the AXI interconnect will take care of the clock domain crossing

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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3 Replies
Moderator
Moderator
295 Views
Registered: ‎11-09-2015

Re: Is an AXI4 Lite peripheral a Soft or Hard IP? and how many input clocks should it have?

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@enriqeat2 wrote:

 

1. I created an AXI4 Lite peripheral, how do I know if this is a soft or hard IP?

[Florent] "I created" -> this is a soft IP

A hard IP is to call an IP which is physically on the silicon. Ex. the Zynq processor.

Even if you do not have it in your vivado design, it will always be in the device

2. The IP block that I created for Zynq performs actions from processes that are synchronized with the 125 Mhz clock of the PL. Now, I see that my AXI IP has another clock input from from the PS, and this could be modified. I want everything on the PL to work with a 125Mhz clock since, it is what´s been designed, but I want to know if I coud have both clocks on the input of the IP, or if I only should have one. does the clock from the PS has anything to do with the internal PL clock for the processes or does it only affect transactions for the Axi communications?. By the way, the whole aplication works when I send comands from SDK.


[Florent] - You can only have one clock input if you need only one. You will need to connect the AXI interconnect with M00_ACLK connected to your clock clk and the AXI interconnect will take care of the clock domain crossing

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Scholar vanmierlo
Scholar
239 Views
Registered: ‎06-10-2008

Re: Is an AXI4 Lite peripheral a Soft or Hard IP? and how many input clocks should it have?

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I think you can also ignore (or even disable) FCLK_CLK0 and use your clk for all clockings.

But where is your clk coming from I wonder. Why not set FCLK_CLK0 to 125 MHz and route it out of the block design and into the PL instead of the other way around?

Visitor enriqeat2
Visitor
228 Views
Registered: ‎01-22-2019

Re: Is an AXI4 Lite peripheral a Soft or Hard IP? and how many input clocks should it have?

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I didn´t have a clear idea of these two clocks, now that i´ve done a bit of research, ended up figuring out the FCLK_CLK0 is actually the clock that runs on the PL, so I´m planning on using it and deleting clk which is practically the same clock.

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