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Participant welcomelm
Participant
196 Views
Registered: ‎01-07-2019

Is it possible to expose a tx_reset signal from AXI 1g/2.5g Ethernet subsystem

For 1588 support, I need to connect m_axis_tx_ts to a datawidth converter->clock converter->axi fifo, the clock domain for m_axis_tx_ts  is tx_mac_aclk, there is supposed to be a tx_reset signal from TEMAC document, but I couldn't find it exposed from AXI 1g/2.5g Ethernet subsystem bus. Need some help to find the reset signal.

 

Thanks

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1 Reply
Moderator
Moderator
169 Views
Registered: ‎07-31-2012

Re: Is it possible to expose a tx_reset signal from AXI 1g/2.5g Ethernet subsystem

Hi @welcomelm,

In AXI Ethernet Subsystem IP there is no tx_reset signal to Tri-Mode EMAC block.

Its just, s_axi_tx_av, gt_clk, m_axis_rx_av and mii/g,ii and rgmii ethernet interface.

 

There areaxi_txd_arstn and axi_txc_arstn ports.

 

Regards

Praveen


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