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Observer mdzialak
Observer
1,234 Views
Registered: ‎04-24-2018

Is it possible to use AXI4 Stream Verification IP directly in HDL hierarchy (without block design) and use its API functions?

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For instance, what should be passed to axi4stream_mst_agent.new() function as a virtual interface axi4stream_vip_if vif?

class axi4stream_mst_agent  extends xil_agent;
//class axi4stream_mst_agent `XIL_AXI4STREAM_PARAM_DECL extends xil_agent;
...

  /*
    Function: new
    Constructor to create an AXI4STREAM Master Agent,~name~ is the name of the instance and axi4stream_vip_if is the interface in the design.
    Please see PG277 for how to find the interface in design hierarchy.
  */
  function new (input string name = "unnamed_axi4stream_mst_agent",virtual interface axi4stream_vip_if `XIL_AXI4STREAM_PARAM_ORDER vif);
...
  endfunction



In example design master agent is created like that:

mst_agent = new("master_vip_agent", DUT.ex_design.axi4stream_vip_mst.inst.IF);

I inserted AXI4Stream Verification IP directly in testbench file:

...
axi4stream_vip_mst axi4stream_vip_mst_test (
  .aclk(clock),                 
  .aresetn(reset),  
  .m_axis_tvalid(mst_tvalid), 
  .m_axis_tready(mst_tready), 
  .m_axis_tdata(mst_tdata),   
  .m_axis_tkeep(mst_tkeep),   
  .m_axis_tlast(mst_tlast)    
);
...

Creating the master agent like that:

mst_agent = new("master vip agent",test_tb.axi4stream_vip_mst_test.inst.IF);

results in the error:
"incompatible complex type assignment"

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1 Solution

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Xilinx Employee
Xilinx Employee
1,376 Views
Registered: ‎10-04-2016

Re: Is it possible to use AXI4 Stream Verification IP directly in HDL hierarchy (without block design) and use its API functions?

Jump to solution

Hi @mdzialak,

See below for how to interact with the VIP once you instantiate it in your test bench.

 

Regards,

Deanna

 

 import axi4stream_vip_pkg::*;

 

module my_testBench ();

 

axi4stream_vip_v1_1_2_top #
(
   .C_AXI4STREAM_SIGNAL_SET(32'h03),
   .C_AXI4STREAM_INTERFACE_MODE(0), //0=master, 2=slave and 1=pass through
   .C_AXI4STREAM_DATA_WIDTH(8),  // in bits
   .C_AXI4STREAM_USER_BITS_PER_BYTE(0),
   .C_AXI4STREAM_ID_WIDTH(0),
   .C_AXI4STREAM_DEST_WIDTH(0),
   .C_AXI4STREAM_USER_WIDTH(0),
   .C_AXI4STREAM_HAS_ARESETN(1)
) axi4stream_vip_mst_tst (
// System Signals
  .aclk(clock),
  .aresetn(reset),
  .aclken(),

// Slave side
  .s_axis_tvalid(),
  .s_axis_tready(),
  .s_axis_tdata(),
  .s_axis_tstrb(),
  .s_axis_tkeep(),
  .s_axis_tlast(),
  .s_axis_tid(),
  .s_axis_tdest(),
  .s_axis_tuser(),

// Master side
  .m_axis_tvalid(mst_tvalid),
  .m_axis_tready(mst_tready),
  .m_axis_tdata(mst_tdata),
  .m_axis_tstrb(),
  .m_axis_tkeep(mst_tkeep),
  .m_axis_tlast(mst_tlast),
  .m_axis_tid(),
  .m_axis_tdest(),
  .m_axis_tuser()
);

 

axis_mst_agent #(3,0,8,0,0,0,0,1) mst_agent;   // parameters must match instantiation exactly

 

initial begin

  mst_agent = new("master stream agent", axi4stream_vip_mst_tst.IF);

  mst_agent.start_master();

 

  /* create and send transactions...*/

end

endmodule

-------------------------------------------------------------------------
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-------------------------------------------------------------------------

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8 Replies
Xilinx Employee
Xilinx Employee
1,143 Views
Registered: ‎10-04-2016

Re: Is it possible to use AXI4 Stream Verification IP directly in HDL hierarchy (without block design) and use its API functions?

Jump to solution

Hi @mdzialak,

It is possible to use the AXI4-Stream VIP as you described. There are a couple of details that might be missing, though.

 

1. The top module for AXI4-Stream VIP is under <Vivado install dir>/data/ip/xilinx/axi4stream_vip_v1_1/hdl/axi4stream_vip_v1_1_vl_rfs.sv.

 

2. The following files are necessary to compile the VIP: xil_common_vip_pkg.sv, axi4stream_vip_if.sv, axi4stream_vip_pkg.sv and axi4stream_vip_axi4streampc.sv. Make sure the compile order is correct. They are located at <Vivado install dir>/data/xilinx_vip/hdl.

 

3. When you instantiate the AXI4-Stream VIP in your test bench, make sure the user parameters are listed and match your design. 

 

axi4stream_vip_v1_1_2_top #
(
   .C_AXI4STREAM_SIGNAL_SET(32'h03),
   .C_AXI4STREAM_INTERFACE_MODE(0), //0=master, 2=slave and 1=pass through
   .C_AXI4STREAM_DATA_WIDTH(8),  // in bits
   .C_AXI4STREAM_USER_BITS_PER_BYTE(0),
   .C_AXI4STREAM_ID_WIDTH(0),
   .C_AXI4STREAM_DEST_WIDTH(0),
   .C_AXI4STREAM_USER_WIDTH(0),
   .C_AXI4STREAM_HAS_ARESETN(1)
) axi4stream_vip_mst_tst (
// System Signals
  .aclk(clock),
  .aresetn(reset),
  .aclken(),

// Slave side
  .s_axis_tvalid(),
  .s_axis_tready(),
  .s_axis_tdata(),
  .s_axis_tstrb(),
  .s_axis_tkeep(),
  .s_axis_tlast(),
  .s_axis_tid(),
  .s_axis_tdest(),
  .s_axis_tuser(),

// Master side
  .m_axis_tvalid(mst_tvalid),
  .m_axis_tready(mst_tready),
  .m_axis_tdata(mst_tdata),
  .m_axis_tstrb(),
  .m_axis_tkeep(mst_tkeep),
  .m_axis_tlast(mst_tlast),
  .m_axis_tid(),
  .m_axis_tdest(),
  .m_axis_tuser()
);

 

Regards, 

 

Deanna

 

 

 

 

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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Xilinx Employee
Xilinx Employee
1,146 Views
Registered: ‎10-04-2016

Re: Is it possible to use AXI4 Stream Verification IP directly in HDL hierarchy (without block design) and use its API functions?

Jump to solution

Hi @mdzialak,

It is possible to use the AXI4-Stream VIP as you described. There are a couple of details that might be missing, though.

 

1. The top module for AXI4-Stream VIP is under <Vivado install dir>/data/ip/xilinx/axi4stream_vip_v1_1/hdl/axi4stream_vip_v1_1_vl_rfs.sv.

 

2. The following files are necessary to compile the VIP:

     - xil_common_vip_macros.svh. It is located at <Vivado install dir>/data/xilinx_vip/hdl/include.

     - xil_common_vip_pkg.sv, axi4stream_vip_pkg.sv, axi4stream_vip_axi4streampc.sv and axi4stream_vip_if.sv. Make sure the compile order is correct. They are located at <Vivado install dir>/data/xilinx_vip/hdl.

 

3. When you instantiate the AXI4-Stream VIP in your test bench, make sure the user parameters are listed and match your design. 

 

axi4stream_vip_v1_1_2_top #
(
   .C_AXI4STREAM_SIGNAL_SET(32'h03),
   .C_AXI4STREAM_INTERFACE_MODE(0), //0=master, 2=slave and 1=pass through
   .C_AXI4STREAM_DATA_WIDTH(8),  // in bits
   .C_AXI4STREAM_USER_BITS_PER_BYTE(0),
   .C_AXI4STREAM_ID_WIDTH(0),
   .C_AXI4STREAM_DEST_WIDTH(0),
   .C_AXI4STREAM_USER_WIDTH(0),
   .C_AXI4STREAM_HAS_ARESETN(1)
) axi4stream_vip_mst_tst (
// System Signals
  .aclk(clock),
  .aresetn(reset),
  .aclken(),

// Slave side
  .s_axis_tvalid(),
  .s_axis_tready(),
  .s_axis_tdata(),
  .s_axis_tstrb(),
  .s_axis_tkeep(),
  .s_axis_tlast(),
  .s_axis_tid(),
  .s_axis_tdest(),
  .s_axis_tuser(),

// Master side
  .m_axis_tvalid(mst_tvalid),
  .m_axis_tready(mst_tready),
  .m_axis_tdata(mst_tdata),
  .m_axis_tstrb(),
  .m_axis_tkeep(mst_tkeep),
  .m_axis_tlast(mst_tlast),
  .m_axis_tid(),
  .m_axis_tdest(),
  .m_axis_tuser()
);

 

4. The C_AXI4STREAM_SIGNAL_SET parameter needs some special attention. Here is the logic to use to set it for your design:

 

C_AXI4STREAM_SIGNAL_SET = 0b’{ (C_AXI4STREAM_USER_WIDTH  >=1)? ==1 :0, (C_AXI4STREAM_DEST_WIDTH  >=1)? ==1 :0,  (C_AXI4STREAM_ID_WIDTH  >=1)? ==1 :0,HAS_TLAST, HAS_TKEEP, HAS_TSTRB, (TDATA_NUM_BYTES >=1)?1:0, HAS_TREADY }

 

From the details you provided, you should set it to 32'b11011 since your interface has TREADY, TDATA, TKEEP, and TLAST.

 

Regards,

 

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Observer mdzialak
Observer
1,127 Views
Registered: ‎04-24-2018

Re: Is it possible to use AXI4 Stream Verification IP directly in HDL hierarchy (without block design) and use its API functions?

Jump to solution

Dear @demarco,

 

thank You very much for the answer.

I unterstand that I should instantiate axi4stream_vip_v1_1_2_top module instead of instantiation template generated for IP Core added to project from IP catalog.
However, I still have no idea how to use AXI4 Stream Verification IP interface API functions after instantiating axi4stream_vip_v1_1_2_top module directly in testbench.
Could You give me some more clues or maybe share some simple example project using AXI4 Stream Verification IP directly in HDL code?

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Xilinx Employee
Xilinx Employee
1,377 Views
Registered: ‎10-04-2016

Re: Is it possible to use AXI4 Stream Verification IP directly in HDL hierarchy (without block design) and use its API functions?

Jump to solution

Hi @mdzialak,

See below for how to interact with the VIP once you instantiate it in your test bench.

 

Regards,

Deanna

 

 import axi4stream_vip_pkg::*;

 

module my_testBench ();

 

axi4stream_vip_v1_1_2_top #
(
   .C_AXI4STREAM_SIGNAL_SET(32'h03),
   .C_AXI4STREAM_INTERFACE_MODE(0), //0=master, 2=slave and 1=pass through
   .C_AXI4STREAM_DATA_WIDTH(8),  // in bits
   .C_AXI4STREAM_USER_BITS_PER_BYTE(0),
   .C_AXI4STREAM_ID_WIDTH(0),
   .C_AXI4STREAM_DEST_WIDTH(0),
   .C_AXI4STREAM_USER_WIDTH(0),
   .C_AXI4STREAM_HAS_ARESETN(1)
) axi4stream_vip_mst_tst (
// System Signals
  .aclk(clock),
  .aresetn(reset),
  .aclken(),

// Slave side
  .s_axis_tvalid(),
  .s_axis_tready(),
  .s_axis_tdata(),
  .s_axis_tstrb(),
  .s_axis_tkeep(),
  .s_axis_tlast(),
  .s_axis_tid(),
  .s_axis_tdest(),
  .s_axis_tuser(),

// Master side
  .m_axis_tvalid(mst_tvalid),
  .m_axis_tready(mst_tready),
  .m_axis_tdata(mst_tdata),
  .m_axis_tstrb(),
  .m_axis_tkeep(mst_tkeep),
  .m_axis_tlast(mst_tlast),
  .m_axis_tid(),
  .m_axis_tdest(),
  .m_axis_tuser()
);

 

axis_mst_agent #(3,0,8,0,0,0,0,1) mst_agent;   // parameters must match instantiation exactly

 

initial begin

  mst_agent = new("master stream agent", axi4stream_vip_mst_tst.IF);

  mst_agent.start_master();

 

  /* create and send transactions...*/

end

endmodule

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

Observer mdzialak
Observer
1,099 Views
Registered: ‎04-24-2018

Re: Is it possible to use AXI4 Stream Verification IP directly in HDL hierarchy (without block design) and use its API functions?

Jump to solution

Dear @demarco,

 

thank You very much for the answer.
I implemented Your solution:

 

import axi4stream_vip_pkg::*;

module axis_realign_tb();

axi4stream_mst_agent #(3,0,8,0,0,0,1) mst_agent;

bit clock;
bit reset;

top uut (.*);

always #10 clock <= ~clock;

initial begin
reset <= 1'b1;
//mst_agent=new("master stream agent", uut.axi4stream_vip_mst_axis_realign.IF);
end
endmodule

Screenshot_2018-05-30_16-23-29.png

 

However, uncommenting line

mst_agent=new("master stream agent", uut.axi4stream_vip_mst_axis_realign.IF);

and launching simulation generates the error:

 

[VRFC 10-900] incompatible complex type assignment

What might be the reason? The incompatibility between interface and virtual interface?

 

class axi4stream_mst_agent ...

function new (input string name = "unnamed_axi4stream_mst_agent",virtual interface axi4stream_vip_if `XIL_AXI4STREAM_PARAM_ORDER vif);

 

module axi4stream_vip_v1_1_2_top # ...

  axi4stream_vip_if #(
    .C_AXI4STREAM_SIGNAL_SET             (C_AXI4STREAM_SIGNAL_SET), 
    .C_AXI4STREAM_DEST_WIDTH             (C_AXI4STREAM_DEST_WIDTH), 
    .C_AXI4STREAM_DATA_WIDTH             (C_AXI4STREAM_DATA_WIDTH),
    .C_AXI4STREAM_ID_WIDTH               (C_AXI4STREAM_ID_WIDTH),
    .C_AXI4STREAM_USER_WIDTH             (C_AXI4STREAM_USER_WIDTH),
    .C_AXI4STREAM_USER_BITS_PER_BYTE     (C_AXI4STREAM_USER_BITS_PER_BYTE),
    .C_AXI4STREAM_HAS_ARESETN            (C_AXI4STREAM_HAS_ARESETN)
  ) IF (
    .ACLK                                (aclk), 
    .ARESET_N                            (aresetn),
    .ACLKEN                              (aclken)
  ); 



 

 

 

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Xilinx Employee
Xilinx Employee
1,094 Views
Registered: ‎10-04-2016

Re: Is it possible to use AXI4 Stream Verification IP directly in HDL hierarchy (without block design) and use its API functions?

Jump to solution

Hi @mdzialak,

There are two situations I can think of where that error might pop up.

 

1. The parameters in this line: 

axi4stream_mst_agent #(3,0,8,0,0,0,1) mst_agent;

don't exactly match the instantiation of the VIP.

2. The path to the interface is incorrect when you "new" the agent. The easiest way to confirm that your path is correct is to start the simulation and have the simulator tell you the path. Please refer to Figure 4-10 in PG277 for an example.

 

Do either of these apply?

 

Regards,

 

Deanna

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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Observer mdzialak
Observer
1,079 Views
Registered: ‎04-24-2018

Re: Is it possible to use AXI4 Stream Verification IP directly in HDL hierarchy (without block design) and use its API functions?

Jump to solution

Hi @demarco,

 

1. Actually, 

axi4stream_mst_agent #(3,0,8,0,0,0,1) mst_agent;

is the proper instantiation of the VIP. The class is called axi4stream_mst_agent (not axis_mst_agent) and it has 7 input arguments (not 8).

2. Path is also correct, launching simulation without master agent instantiation prompts info:

Xilinx AXI4STREAM VIP Found at Path: axis_realign_tb.uut.axi4stream_vip_mst_axis_realign

 

In this discussion:

https://forums.xilinx.com/t5/Simulation-and-Verification/VRFC-10-93-IF-is-not-declared-under-prefix-inst/td-p/820830/page/2

reinstalling Vivado appeared to be a solution...


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Observer mdzialak
Observer
1,071 Views
Registered: ‎04-24-2018

Re: Is it possible to use AXI4 Stream Verification IP directly in HDL hierarchy (without block design) and use its API functions?

Jump to solution

Complex type assignment incompatibility was the result of improper value of C_AXI4STREAM_SIGNAL_SET parameter.

Improved, working version:

axi4stream_mst_agent #(25,0,8,0,0,0,1) mst_agent;
C_AXI4STREAM_SIGNAL_SET = 0b’{ (C_AXI4STREAM_USER_WIDTH  >=1)? ==1 :0, (C_AXI4STREAM_DEST_WIDTH  >=1)? ==1 :0,  (C_AXI4STREAM_ID_WIDTH  >=1)? ==1 :0,HAS_TLAST, HAS_TKEEP, HAS_TSTRB, (TDATA_NUM_BYTES >=1)?1:0, HAS_TREADY } = 'b00011001 = 'd25

@demarco, thank You very much for the patience!

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