UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor jyro
Visitor
4,950 Views
Registered: ‎06-22-2010

Issue accessing DDR (MPMC) access via PowerPC (PLB)

In my EDK project, I have an MPMC pcore to access two Micron MT46V16M16BG-6.  I believe I have the MPMC configured correctly, but can not figure out what is causing problems.  The symptoms that I observe is that the PowerPC hangs while attempting to access DDR (reads and/or writes).  

When I configure the FPGA, I do not initialize the BRAMs, so no software application runs on the PowerPC.  Through Chipscope, I see that the MPMC signal, InitDone, does indeed go HI when the FPGA is first configured.  However, as soon as I run the software application and the PowerPC attempts a DDR access, InitDone drops.  Also, the output at my terminal just hangs.
As a troubleshooting step, I have an NPI interface sitting outside of EDK, on my top-level ISE project.  I have used this interface to read/write and do see that the read/write transaction completes.
My guess is that, given that I can read/write via the NPI interface, the MPMC is configured correctly but I'm running out of ideas.  Any suggestions would be appreciated.
Thanks,
Jairo
MHS portion that pertains to MPMC:
# clocks
 PORT sys_clk_200_pin = proc_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 200000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
 PORT sys_clk_100_pin = sys_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_clk_100_90_pin = sys_clk_s90, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT dcm_locked_pin = Dcm_all_locked, DIR = I
# DDR Interface
 PORT fpga_0_DDR_SDRAM_Clk_pin = fpga_0_DDR_SDRAM_Clk, DIR = O
 PORT fpga_0_DDR_SDRAM_Clk_n_pin = fpga_0_DDR_SDRAM_Clk_n, DIR = O
 PORT fpga_0_DDR_SDRAM_Addr_pin = fpga_0_DDR_SDRAM_Addr, DIR = O, VEC = [12:0]
 PORT fpga_0_DDR_SDRAM_BankAddr_pin = fpga_0_DDR_SDRAM_BankAddr, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_CAS_n_pin = fpga_0_DDR_SDRAM_CAS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_CE_pin = fpga_0_DDR_SDRAM_CE, DIR = O
 PORT fpga_0_DDR_SDRAM_CS_n_pin = fpga_0_DDR_SDRAM_CS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_RAS_n_pin = fpga_0_DDR_SDRAM_RAS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_WE_n_pin = fpga_0_DDR_SDRAM_WE_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DM_pin = fpga_0_DDR_SDRAM_DM, DIR = O, VEC = [3:0]
 PORT fpga_0_DDR_SDRAM_DQS = fpga_0_DDR_SDRAM_DQS, DIR = IO, VEC = [3:0]
 PORT fpga_0_DDR_SDRAM_DQ = fpga_0_DDR_SDRAM_DQ, DIR = IO, VEC = [31:0]
 
# MPMC, NPI Interface
 PORT DDR_SDRAM_PIM1_AddrReq_pin = DDR_SDRAM_PIM1_AddrReq, DIR = I
 PORT DDR_SDRAM_PIM1_Addr_pin = DDR_SDRAM_PIM1_Addr, DIR = I, VEC = [31:0]
 PORT DDR_SDRAM_PIM1_RNW_pin = DDR_SDRAM_PIM1_RNW, DIR = I
 PORT DDR_SDRAM_PIM1_Size_pin = DDR_SDRAM_PIM1_Size, DIR = I, VEC = [3:0]
 PORT DDR_SDRAM_PIM1_RdModWr_pin = DDR_SDRAM_PIM1_RdModWr, DIR = I
 PORT DDR_SDRAM_PIM1_InitDone_pin = DDR_SDRAM_PIM1_InitDone, DIR = O
 PORT DDR_SDRAM_PIM1_AddrAck_pin = DDR_SDRAM_PIM1_AddrAck, DIR = O
 PORT DDR_SDRAM_PIM1_WrFIFO_Data_pin = DDR_SDRAM_PIM1_WrFIFO_Data, DIR = I, VEC = [63:0]
 PORT DDR_SDRAM_PIM1_WrFIFO_BE_pin = DDR_SDRAM_PIM1_WrFIFO_BE, DIR = I, VEC = [7:0]
 PORT DDR_SDRAM_PIM1_WrFIFO_Push_pin = DDR_SDRAM_PIM1_WrFIFO_Push, DIR = I
 PORT DDR_SDRAM_PIM1_WrFIFO_Flush_pin = DDR_SDRAM_PIM1_WrFIFO_Flush, DIR = I
 PORT DDR_SDRAM_PIM1_WrFIFO_Empty_pin = DDR_SDRAM_PIM1_WrFIFO_Empty, DIR = O
 PORT DDR_SDRAM_PIM1_WrFIFO_AlmostFull_pin = DDR_SDRAM_PIM1_WrFIFO_AlmostFull, DIR = O
 PORT DDR_SDRAM_PIM1_RdFIFO_Pop_pin = DDR_SDRAM_PIM1_RdFIFO_Pop, DIR = I
 PORT DDR_SDRAM_PIM1_RdFIFO_Flush_pin = DDR_SDRAM_PIM1_RdFIFO_Flush, DIR = I
 PORT DDR_SDRAM_PIM1_RdFIFO_Data_pin = DDR_SDRAM_PIM1_RdFIFO_Data, DIR = O, VEC = [63:0]
 PORT DDR_SDRAM_PIM1_RdFIFO_RdWdAddr_pin = DDR_SDRAM_PIM1_RdFIFO_RdWdAddr, DIR = O, VEC = [3:0]
 PORT DDR_SDRAM_PIM1_RdFIFO_Empty_pin = DDR_SDRAM_PIM1_RdFIFO_Empty, DIR = O
 PORT DDR_SDRAM_PIM1_RdFIFO_Latency_pin = DDR_SDRAM_PIM1_RdFIFO_Latency, DIR = O, VEC = [1:0]
 
# MPMC InitDone
 PORT DDR_SDRAM_MPMC_InitDone_pin = DDR_SDRAM_MPMC_InitDone, DIR = O
BEGIN plb_v46
 PARAMETER INSTANCE = plb
 PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
 PARAMETER HW_VER = 1.03.a
 PORT PLB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END
BEGIN mpmc
 PARAMETER INSTANCE = DDR_SDRAM
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_MPMC_BASEADDR = 0x00000000
 PARAMETER C_MPMC_HIGHADDR = 0x03FFFFFF
 PARAMETER C_MEM_PARTNO = CUSTOM
 PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
 PARAMETER C_MEM_TYPE = DDR
 PARAMETER C_MEM_DATA_WIDTH = 32
 PARAMETER C_MEM_PART_DATA_WIDTH = 16
 PARAMETER C_MEM_PART_CAS_A_FMAX = 166
 PARAMETER C_MEM_PART_CAS_A = 2.5
 PARAMETER C_MEM_PART_TRAS = 42000
 PARAMETER C_MEM_PART_TRASMAX = 70000000
 PARAMETER C_MEM_PART_TRC = 60000
 PARAMETER C_MEM_PART_CAS_B_FMAX = 166
 PARAMETER C_MEM_PART_CAS_B = 2.5
 PARAMETER C_MEM_PART_TWR = 15000
 PARAMETER C_MEM_PART_TRRD = 12000
 PARAMETER C_MEM_PART_TRCD = 15000
 PARAMETER C_MEM_PART_TREFI = 7800000
 PARAMETER C_MEM_PART_TRFC = 72000
 PARAMETER C_MEM_PART_TRP = 15000
 PARAMETER C_PIM1_BASETYPE = 4
 PARAMETER C_NUM_PORTS = 2
 BUS_INTERFACE SPLB0 = plb
 PORT MPMC_Clk_200MHz = proc_clk_s
 PORT MPMC_Clk90 = sys_clk_s90
 PORT MPMC_Clk0 = sys_clk_s
 PORT MPMC_Rst = sys_periph_reset
 PORT DDR_DQS = fpga_0_DDR_SDRAM_DQS
 PORT DDR_DM = fpga_0_DDR_SDRAM_DM
 PORT DDR_DQ = fpga_0_DDR_SDRAM_DQ
 PORT DDR_Addr = fpga_0_DDR_SDRAM_Addr
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_BankAddr
 PORT DDR_WE_n = fpga_0_DDR_SDRAM_WE_n
 PORT DDR_CAS_n = fpga_0_DDR_SDRAM_CAS_n
 PORT DDR_RAS_n = fpga_0_DDR_SDRAM_RAS_n
 PORT DDR_CS_n = fpga_0_DDR_SDRAM_CS_n
 PORT DDR_CE = fpga_0_DDR_SDRAM_CE
 PORT DDR_Clk_n = fpga_0_DDR_SDRAM_Clk_n
 PORT DDR_Clk = fpga_0_DDR_SDRAM_Clk
 PORT PIM1_AddrReq = DDR_SDRAM_PIM1_AddrReq
 PORT PIM1_Addr = DDR_SDRAM_PIM1_Addr
 PORT PIM1_RNW = DDR_SDRAM_PIM1_RNW
 PORT PIM1_Size = DDR_SDRAM_PIM1_Size
 PORT PIM1_RdModWr = DDR_SDRAM_PIM1_RdModWr
 PORT PIM1_InitDone = DDR_SDRAM_PIM1_InitDone
 PORT PIM1_AddrAck = DDR_SDRAM_PIM1_AddrAck
 PORT PIM1_WrFIFO_Data = DDR_SDRAM_PIM1_WrFIFO_Data
 PORT PIM1_WrFIFO_BE = DDR_SDRAM_PIM1_WrFIFO_BE
 PORT PIM1_WrFIFO_Push = DDR_SDRAM_PIM1_WrFIFO_Push
 PORT PIM1_WrFIFO_Flush = DDR_SDRAM_PIM1_WrFIFO_Flush
 PORT PIM1_WrFIFO_Empty = DDR_SDRAM_PIM1_WrFIFO_Empty
 PORT PIM1_WrFIFO_AlmostFull = DDR_SDRAM_PIM1_WrFIFO_AlmostFull
 PORT PIM1_RdFIFO_Pop = DDR_SDRAM_PIM1_RdFIFO_Pop
 PORT PIM1_RdFIFO_Flush = DDR_SDRAM_PIM1_RdFIFO_Flush
 PORT PIM1_RdFIFO_Data = DDR_SDRAM_PIM1_RdFIFO_Data
 PORT PIM1_RdFIFO_RdWdAddr = DDR_SDRAM_PIM1_RdFIFO_RdWdAddr
 PORT PIM1_RdFIFO_Empty = DDR_SDRAM_PIM1_RdFIFO_Empty
 PORT PIM1_RdFIFO_Latency = DDR_SDRAM_PIM1_RdFIFO_Latency
 PORT MPMC_InitDone = DDR_SDRAM_MPMC_InitDone
END

 

In my EDK project, I have an MPMC pcore to access two Micron MT46V16M16BG-6.  I believe I have the MPMC configured correctly, but can not figure out what is causing problems.  The symptoms that I observe is that the PowerPC hangs while attempting to access DDR (reads and/or writes).  

 

When I configure the FPGA, I do not initialize the BRAMs, so no software application runs on the PowerPC.  Through Chipscope, I see that the MPMC signal, InitDone, does indeed go HI when the FPGA is first configured.  However, as soon as I run the software application and the PowerPC attempts a DDR access, InitDone drops.  Also, the output at my terminal just hangs.


As a troubleshooting step, I have an NPI interface sitting outside of EDK, on my top-level ISE project.  I have used this interface to read/write and do see that the read/write transaction completes.
My guess is that, given that I can read/write via the NPI interface, the MPMC is configured correctly but I'm running out of ideas.  Any suggestions would be appreciated.

 

Thanks

 

 

####################################################

# MHS portion that pertains to MPMC:

####################################################

# clocks

 PORT sys_clk_200_pin = proc_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 200000000

 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST

 PORT sys_clk_100_pin = sys_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000

 PORT sys_clk_100_90_pin = sys_clk_s90, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000

 PORT dcm_locked_pin = Dcm_all_locked, DIR = I

 

# DDR Interface

 PORT fpga_0_DDR_SDRAM_Clk_pin = fpga_0_DDR_SDRAM_Clk, DIR = O

 PORT fpga_0_DDR_SDRAM_Clk_n_pin = fpga_0_DDR_SDRAM_Clk_n, DIR = O

 PORT fpga_0_DDR_SDRAM_Addr_pin = fpga_0_DDR_SDRAM_Addr, DIR = O, VEC = [12:0]

 PORT fpga_0_DDR_SDRAM_BankAddr_pin = fpga_0_DDR_SDRAM_BankAddr, DIR = O, VEC = [1:0]

 PORT fpga_0_DDR_SDRAM_CAS_n_pin = fpga_0_DDR_SDRAM_CAS_n, DIR = O

 PORT fpga_0_DDR_SDRAM_CE_pin = fpga_0_DDR_SDRAM_CE, DIR = O

 PORT fpga_0_DDR_SDRAM_CS_n_pin = fpga_0_DDR_SDRAM_CS_n, DIR = O

 PORT fpga_0_DDR_SDRAM_RAS_n_pin = fpga_0_DDR_SDRAM_RAS_n, DIR = O

 PORT fpga_0_DDR_SDRAM_WE_n_pin = fpga_0_DDR_SDRAM_WE_n, DIR = O

 PORT fpga_0_DDR_SDRAM_DM_pin = fpga_0_DDR_SDRAM_DM, DIR = O, VEC = [3:0]

 PORT fpga_0_DDR_SDRAM_DQS = fpga_0_DDR_SDRAM_DQS, DIR = IO, VEC = [3:0]

 PORT fpga_0_DDR_SDRAM_DQ = fpga_0_DDR_SDRAM_DQ, DIR = IO, VEC = [31:0]

 

# MPMC, NPI Interface

 PORT DDR_SDRAM_PIM1_AddrReq_pin = DDR_SDRAM_PIM1_AddrReq, DIR = I

 PORT DDR_SDRAM_PIM1_Addr_pin = DDR_SDRAM_PIM1_Addr, DIR = I, VEC = [31:0]

 PORT DDR_SDRAM_PIM1_RNW_pin = DDR_SDRAM_PIM1_RNW, DIR = I

 PORT DDR_SDRAM_PIM1_Size_pin = DDR_SDRAM_PIM1_Size, DIR = I, VEC = [3:0]

 PORT DDR_SDRAM_PIM1_RdModWr_pin = DDR_SDRAM_PIM1_RdModWr, DIR = I

 PORT DDR_SDRAM_PIM1_InitDone_pin = DDR_SDRAM_PIM1_InitDone, DIR = O

 PORT DDR_SDRAM_PIM1_AddrAck_pin = DDR_SDRAM_PIM1_AddrAck, DIR = O

 PORT DDR_SDRAM_PIM1_WrFIFO_Data_pin = DDR_SDRAM_PIM1_WrFIFO_Data, DIR = I, VEC = [63:0]

 PORT DDR_SDRAM_PIM1_WrFIFO_BE_pin = DDR_SDRAM_PIM1_WrFIFO_BE, DIR = I, VEC = [7:0]

 PORT DDR_SDRAM_PIM1_WrFIFO_Push_pin = DDR_SDRAM_PIM1_WrFIFO_Push, DIR = I

 PORT DDR_SDRAM_PIM1_WrFIFO_Flush_pin = DDR_SDRAM_PIM1_WrFIFO_Flush, DIR = I

 PORT DDR_SDRAM_PIM1_WrFIFO_Empty_pin = DDR_SDRAM_PIM1_WrFIFO_Empty, DIR = O

 PORT DDR_SDRAM_PIM1_WrFIFO_AlmostFull_pin = DDR_SDRAM_PIM1_WrFIFO_AlmostFull, DIR = O

 PORT DDR_SDRAM_PIM1_RdFIFO_Pop_pin = DDR_SDRAM_PIM1_RdFIFO_Pop, DIR = I

 PORT DDR_SDRAM_PIM1_RdFIFO_Flush_pin = DDR_SDRAM_PIM1_RdFIFO_Flush, DIR = I

 PORT DDR_SDRAM_PIM1_RdFIFO_Data_pin = DDR_SDRAM_PIM1_RdFIFO_Data, DIR = O, VEC = [63:0]

 PORT DDR_SDRAM_PIM1_RdFIFO_RdWdAddr_pin = DDR_SDRAM_PIM1_RdFIFO_RdWdAddr, DIR = O, VEC = [3:0]

 PORT DDR_SDRAM_PIM1_RdFIFO_Empty_pin = DDR_SDRAM_PIM1_RdFIFO_Empty, DIR = O

 PORT DDR_SDRAM_PIM1_RdFIFO_Latency_pin = DDR_SDRAM_PIM1_RdFIFO_Latency, DIR = O, VEC = [1:0]

 

# MPMC InitDone

 PORT DDR_SDRAM_MPMC_InitDone_pin = DDR_SDRAM_MPMC_InitDone, DIR = O

 

 

 

BEGIN plb_v46

 PARAMETER INSTANCE = plb

 PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100

 PARAMETER HW_VER = 1.03.a

 PORT PLB_Clk = sys_clk_s

 PORT SYS_Rst = sys_bus_reset

END

 

 

BEGIN mpmc

 PARAMETER INSTANCE = DDR_SDRAM

 PARAMETER HW_VER = 4.03.a

 PARAMETER C_MPMC_BASEADDR = 0x00000000

 PARAMETER C_MPMC_HIGHADDR = 0x03FFFFFF

 PARAMETER C_MEM_PARTNO = CUSTOM

 PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000

 PARAMETER C_MEM_TYPE = DDR

 PARAMETER C_MEM_DATA_WIDTH = 32

 PARAMETER C_MEM_PART_DATA_WIDTH = 16

 PARAMETER C_MEM_PART_CAS_A_FMAX = 166

 PARAMETER C_MEM_PART_CAS_A = 2.5

 PARAMETER C_MEM_PART_TRAS = 42000

 PARAMETER C_MEM_PART_TRASMAX = 70000000

 PARAMETER C_MEM_PART_TRC = 60000

 PARAMETER C_MEM_PART_CAS_B_FMAX = 166

 PARAMETER C_MEM_PART_CAS_B = 2.5

 PARAMETER C_MEM_PART_TWR = 15000

 PARAMETER C_MEM_PART_TRRD = 12000

 PARAMETER C_MEM_PART_TRCD = 15000

 PARAMETER C_MEM_PART_TREFI = 7800000

 PARAMETER C_MEM_PART_TRFC = 72000

 PARAMETER C_MEM_PART_TRP = 15000

 PARAMETER C_PIM1_BASETYPE = 4

 PARAMETER C_NUM_PORTS = 2

 BUS_INTERFACE SPLB0 = plb

 PORT MPMC_Clk_200MHz = proc_clk_s

 PORT MPMC_Clk90 = sys_clk_s90

 PORT MPMC_Clk0 = sys_clk_s

 PORT MPMC_Rst = sys_periph_reset

 PORT DDR_DQS = fpga_0_DDR_SDRAM_DQS

 PORT DDR_DM = fpga_0_DDR_SDRAM_DM

 PORT DDR_DQ = fpga_0_DDR_SDRAM_DQ

 PORT DDR_Addr = fpga_0_DDR_SDRAM_Addr

 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_BankAddr

 PORT DDR_WE_n = fpga_0_DDR_SDRAM_WE_n

 PORT DDR_CAS_n = fpga_0_DDR_SDRAM_CAS_n

 PORT DDR_RAS_n = fpga_0_DDR_SDRAM_RAS_n

 PORT DDR_CS_n = fpga_0_DDR_SDRAM_CS_n

 PORT DDR_CE = fpga_0_DDR_SDRAM_CE

 PORT DDR_Clk_n = fpga_0_DDR_SDRAM_Clk_n

 PORT DDR_Clk = fpga_0_DDR_SDRAM_Clk

 PORT PIM1_AddrReq = DDR_SDRAM_PIM1_AddrReq

 PORT PIM1_Addr = DDR_SDRAM_PIM1_Addr

 PORT PIM1_RNW = DDR_SDRAM_PIM1_RNW

 PORT PIM1_Size = DDR_SDRAM_PIM1_Size

 PORT PIM1_RdModWr = DDR_SDRAM_PIM1_RdModWr

 PORT PIM1_InitDone = DDR_SDRAM_PIM1_InitDone

 PORT PIM1_AddrAck = DDR_SDRAM_PIM1_AddrAck

 PORT PIM1_WrFIFO_Data = DDR_SDRAM_PIM1_WrFIFO_Data

 PORT PIM1_WrFIFO_BE = DDR_SDRAM_PIM1_WrFIFO_BE

 PORT PIM1_WrFIFO_Push = DDR_SDRAM_PIM1_WrFIFO_Push

 PORT PIM1_WrFIFO_Flush = DDR_SDRAM_PIM1_WrFIFO_Flush

 PORT PIM1_WrFIFO_Empty = DDR_SDRAM_PIM1_WrFIFO_Empty

 PORT PIM1_WrFIFO_AlmostFull = DDR_SDRAM_PIM1_WrFIFO_AlmostFull

 PORT PIM1_RdFIFO_Pop = DDR_SDRAM_PIM1_RdFIFO_Pop

 PORT PIM1_RdFIFO_Flush = DDR_SDRAM_PIM1_RdFIFO_Flush

 PORT PIM1_RdFIFO_Data = DDR_SDRAM_PIM1_RdFIFO_Data

 PORT PIM1_RdFIFO_RdWdAddr = DDR_SDRAM_PIM1_RdFIFO_RdWdAddr

 PORT PIM1_RdFIFO_Empty = DDR_SDRAM_PIM1_RdFIFO_Empty

 PORT PIM1_RdFIFO_Latency = DDR_SDRAM_PIM1_RdFIFO_Latency

 PORT MPMC_InitDone = DDR_SDRAM_MPMC_InitDone

END

 

 

 

InitDone_goesLO.bmp
0 Kudos
5 Replies
Observer gs_cmans
Observer
4,945 Views
Registered: ‎04-19-2010

Re: Issue accessing DDR (MPMC) access via PowerPC (PLB)

you can try accessing DDR memory space through PPC JTAG interface from XMD console to make sure MPMC on PLB works,

0 Kudos
Visitor jyro
Visitor
4,929 Views
Registered: ‎06-22-2010

Re: Issue accessing DDR (MPMC) access via PowerPC (PLB)

Hey gs_cmsans, I tried reading/writing via XMD (using mrd/mwr) like you suggested.  The commands do execute but the data I read back is not what I expected.  In Chipscope I have tried triggering on SPLB0_PLB_PAValid or SPLB_Sl_rdDAck but the trigger never executes. Any ideas?

0 Kudos
Visitor jyro
Visitor
4,927 Views
Registered: ‎06-22-2010

Re: Issue accessing DDR (MPMC) access via PowerPC (PLB)

I just learned something new.   MPMC_InitDone goes LO when I download an elf to memory.  Whether I access DDR or not in my software application is irrelevant to the issue.  Using Chipscope I see that MPMC_InitDone drops as I download the app.  I've tried downloading the elf via XMD and XPS SDK and observe the same symptom. Also, MPMC_InitDone then remains LO until I re-program the FPGA.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
4,915 Views
Registered: ‎07-30-2007

Re: Issue accessing DDR (MPMC) access via PowerPC (PLB)

By default, XMD issues a reset of the processor system, which is why your init_done goes low.  This option can be disabled.

Upon continued dows or resets, does init_done ever come back?

0 Kudos
Visitor jyro
Visitor
4,910 Views
Registered: ‎06-22-2010

Re: Issue accessing DDR (MPMC) access via PowerPC (PLB)

Hi Dylan, 

No, init_done never comes back following the reset.  I disabled the -reset_on_run debugconfig option and I'm able to download an run the program.  This time InitDone remains HI but the PowerPC still locks up attempting to access DDR.


I've experimented with the "rst" xmd command and do notice InitDone going LO every time I issue a rst. 

0 Kudos