UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
4,355 Views
Registered: ‎06-21-2013

Issue with Simulating the AXI GPIO core

Hi all,

 

I have been trying to simulate a custom host master bridge to AXI4 lite slave.  If we use our AXI4 lite test cores for the termination AXI4 lite devices the bridge works fine with no errors.  However, if we add a Xilinx AXI GPIO core and try to write (reading is fine) we find that the GPIO core does not assert the BVALID signal on the second write.  Remove all other AXI Test cores so we only  have our custom bridge connected by the AXI interconnect to only one AXI GPIO device, no problems.

 

If we try to use two AXI GPIO cores, the issue returns.  It looks like there is potentially an issue with the generate simulation products for the AXI GPIO.   Unfortunately, we don't have a license for the Zynq Base system Simulation device so we are unable to test (simulate)  independent of our custom hardware.

 

Vivado Version 2014.2

 

 

Regards

 

 

Walter

 

 

0 Kudos
1 Reply
Moderator
Moderator
4,323 Views
Registered: ‎04-17-2011

Re: Issue with Simulating the AXI GPIO core

Can you provide a testcase?
Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos