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Registered: ‎04-03-2017

LVDS logic inversion best method?

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I have a situation where routing differential traces for LVDS on the pcb to a zynq module would be easiest if I connected them "inverted" (i.e. p->n and n->p). These LVDS lines are received data and clock lines for Camera Link with my hardware acting as a frame grabber. They will go into the PL into a selectio module to deserialize the data. These are LVDS_25 lines employing the on-chip differential termination.

 

Based on the inputs for the selectio camera link module which are differential (I have to connect the p and n lines separately in a block diagram view) it appears that I could connect them inverted in the design and thus achieve the proper mapping to have the correct logical values enter the selectio module. 

 

What I would like to know is: is this a good way to handle an issue like this? Is there a better or more standard way to achieve this inversion to avoid difficult pcb routing? 

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Registered: ‎01-08-2012

Re: LVDS logic inversion best method?

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I often do P/N swaps on my designs, for both differential SelectIO (e.g. LVDS) and the CML ports on the high speed transceivers.  All that happens (for the SelectIO) is that the logic signal inside your design is inverted.

 

The trick is that if you (or the IP you're instantiating) instantiates an IBUFDS (or equivalent), the IBUFDS 'I' input must go to the 'p' pin on the FPGA, and the IBUFDS 'IB' input must go to the 'n' pin on the FPGA.  There is no other possible way of connecting these.

This means that you probably can't swap the P/N signals (i.e. connect them p->n and n->p) between your top level ports and the IP you're instantiating.  The correct way to do this is to add a logic inversion ("not") after the IBUFDS inside the IP, or (more likely) after the ISERDES inside the IP (since you can't put logic between an IBUF and an IDDR or ISERDES).  Depending on the speed, you might need to put the inversion after a pipelining stage after the ISERDES instead.

 

I am unfamiliar with the particular IP you are using, but you might:

  1. Find that it already has a generic / parameter that controls inversion on its differential ports.
  2. Find that the Wizard that generates it can be told about the inversions.
  3. Find that you can hack in such a control (into the generated RTL).

 

As an aside, I use a top level generic to control inversion for each differential port on my designs.  I can simulate without inversion (which makes the sim easier to understand!) and I can tell the PCB layout person to P/N swap wherever it makes sense.  After the PCB layout is finished I use software to extract the swap information from the PCB EDIF and get the correct values for the generics.  (Actually it does more than that - it writes the entire entity port declaration as well as the FPGA pinout constraints file, which means my PCB and my FPGA ports always match.)

 

Regards,

Allan

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5,054 Views
Registered: ‎01-08-2012

Re: LVDS logic inversion best method?

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I often do P/N swaps on my designs, for both differential SelectIO (e.g. LVDS) and the CML ports on the high speed transceivers.  All that happens (for the SelectIO) is that the logic signal inside your design is inverted.

 

The trick is that if you (or the IP you're instantiating) instantiates an IBUFDS (or equivalent), the IBUFDS 'I' input must go to the 'p' pin on the FPGA, and the IBUFDS 'IB' input must go to the 'n' pin on the FPGA.  There is no other possible way of connecting these.

This means that you probably can't swap the P/N signals (i.e. connect them p->n and n->p) between your top level ports and the IP you're instantiating.  The correct way to do this is to add a logic inversion ("not") after the IBUFDS inside the IP, or (more likely) after the ISERDES inside the IP (since you can't put logic between an IBUF and an IDDR or ISERDES).  Depending on the speed, you might need to put the inversion after a pipelining stage after the ISERDES instead.

 

I am unfamiliar with the particular IP you are using, but you might:

  1. Find that it already has a generic / parameter that controls inversion on its differential ports.
  2. Find that the Wizard that generates it can be told about the inversions.
  3. Find that you can hack in such a control (into the generated RTL).

 

As an aside, I use a top level generic to control inversion for each differential port on my designs.  I can simulate without inversion (which makes the sim easier to understand!) and I can tell the PCB layout person to P/N swap wherever it makes sense.  After the PCB layout is finished I use software to extract the swap information from the PCB EDIF and get the correct values for the generics.  (Actually it does more than that - it writes the entire entity port declaration as well as the FPGA pinout constraints file, which means my PCB and my FPGA ports always match.)

 

Regards,

Allan

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Registered: ‎01-08-2012

Re: LVDS logic inversion best method?

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"since you can't put logic between an IBUF and an IDDR or ISERDES"

 

I just saw that in UG471 figures 3-1 (ISERDES), 2-4 (ILOGICE3) and 2-3 (ILOGICE2) there is what appears to be a programmable inversion on the D input of those functional blocks.

I didn't notice a corresponding inverter on the OSERDES and OLOGIC though.

 

UG471 didn't mention any attributes that could be used to control the inversion.

 

EDIT: the Unisim library source for ISERDESE2, IDDR and IDDR_2CLK has a generic called "IS_D_INVERTED" which sounds promising.  There are corresponding generics on ODDR, ODDRE1, OSERDESE2, but curiously not on OSERDESE3.

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Registered: ‎04-03-2017

Re: LVDS logic inversion best method?

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Thank you so much -- this is a very helpful and detailed answer.

 

>Find that you can hack in such a control (into the generated RTL).

 

I have noticed that the IBUFDS can apparently be replaced by an IBUFDS_DIFF_OUT which would give both logical outputs to use presumably. However the note that goes with IBUFDS_DIFF_OUT states that it should be used by experienced Xilinx designers only (I'm far from that). So it seems possible to do this LVDS inversion in a variety of ways-- but in my case not as easily as doing it on the pcb design unfortunately. 

 

Thanks again!

 

 

 

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