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Observer timing@idt
Observer
286 Views
Registered: ‎06-07-2018

Looking for design advice for a simple time stamping unit

I already have a RTC with second and ns ports. I need to design a time stamping unit, which would record the RTC's second and ns ports based on an external trigger, such as a pulse signal from an external port.

Thanks

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5 Replies
Scholar dgisselq
Scholar
279 Views
Registered: ‎05-21-2015

Re: Looking for design advice for a simple time stamping unit

Sounds like a fun project.  What design advice do you need?

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Scholar drjohnsmith
Scholar
256 Views
Registered: ‎07-09-2009

Re: Looking for design advice for a simple time stamping unit

A big rotating drum , powered of a mains motoor, with a pencil on it would make a nice regular tick for you...

 

To come back though,

 

You really need to give us a lot more detils as to what you know how to do already,

    Its no good us just saying add a timmer peripheral to the PL side and output via th eethernet over a UDP link !

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Adventurer
Adventurer
244 Views
Registered: ‎01-27-2008

Re: Looking for design advice for a simple time stamping unit

Hi,

I've done this before with an "external trigger" being the pps (exactly a second) from a GPS system.

SW would pre-load this register with the incoming second count that would correspond to the pps arrival, then your timer is resychronized every second (or few depending on when you use the pre-load register to reset your counter).

Then you have an accumulator that is a free-running counter at the clock rate  - adding your exact clock time every 'tick' to the accumulator (perhaps at sub-ps level for increased accuracy over each second at the ns resolution level).

Truncate to the ns level when reading the value, but maintain accumulation below this level (as mentioned to the sub-ps level).  if your sub-second counter is 32b you get < 1 ns resolution in the accumulator, 48b counter gives around fs resuolution.

In example if your free running clock is 100 MHz you'll accumulate 10E-9 every count.  This seems like a tidy number but it is not neatly captured in binary (2^-1, 2^-2, 2^(-3), etc so you'll have to represent your accumulated tick count in an approximation ( in base 2 vs base 10). So a longer accumulator register provides better accuracy between updates (SW reset through trigger- in my example pps).

Have fun with it!

 

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Observer timing@idt
Observer
234 Views
Registered: ‎06-07-2018

Re: Looking for design advice for a simple time stamping unit

Thanks all for replying. Below is more detail

Attached is the RTC that I am using for 1588 support for AXI ethernet subsystem on the PL side.

Now I need a time stamping unit on the PL side that take a shot of both s_field and ns_field of RTC base on an external trigger, which is a 1 pps signal from somewhere else.

I need this to be done 100% FPGA without sw intervention. SW will only read the TSU to find out shot of s_field and ns_field every second. 

 

Thanks

1588_timer.png
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Scholar dgisselq
Scholar
231 Views
Registered: ‎05-21-2015

Re: Looking for design advice for a simple time stamping unit

Ahh ... now I get it.  You are looking for something like this--a piece of code that tracks an input PPS signal and produces a ns level--accuracy output.  (Ok, so it's only good to about 100ns or so, but it gets pretty close)

Dan