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Newbie 2p718
Newbie
2,160 Views
Registered: ‎01-08-2017

MIO[8:7] special requirements contradiction

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UG585 (v1.11), page 51 states "MIO Pins [8:7] are Outputs: These MIO pins are available as output only. GPIO channels 7 and 8 can only be configured as outputs".

 

Yet in UG585 (v1.11), page 180, the MIO[8:7] are configured as inputs.

 

Can someone please give a definitive answer as to what MIO[8:7] can do?

 

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Community Manager
Community Manager
3,894 Views
Registered: ‎07-23-2015

Re: MIO[8:7] special requirements contradiction

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@2p718 Table 6-9 seems to be incorrect. MIO 7 is not used in QSPI while MIO 8 is QSPI FB clk whose operation is explained in page 353. Check Page 358 12.5.2 & table 12-9 on page 361. they should clear up your queries. 

 

Check Table 6-18, Table 6-19 on these pin operation for other modes.

- Giri
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There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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2 Replies
Community Manager
Community Manager
3,895 Views
Registered: ‎07-23-2015

Re: MIO[8:7] special requirements contradiction

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@2p718 Table 6-9 seems to be incorrect. MIO 7 is not used in QSPI while MIO 8 is QSPI FB clk whose operation is explained in page 353. Check Page 358 12.5.2 & table 12-9 on page 361. they should clear up your queries. 

 

Check Table 6-18, Table 6-19 on these pin operation for other modes.

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
Xilinx Employee
Xilinx Employee
2,122 Views
Registered: ‎07-23-2012

Re: MIO[8:7] special requirements contradiction

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Giri is correct. MIO[8] should be an output and Zynq7 Processing System IP configuration GUI also confirms the same-

 

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