05-13-2014 06:55 AM
Can anyone give me some hints on making a AXI (stream or memory mapped) to native FIFO. The IP catalogue has options for native and AXI ports but not a way to mix them. I would like to move data from the PS to PL through a FIFO.
I am guessing that I should use the stream type because it would have flow control (full, empty ect)
I am using Vivado 2014.1 web edition
05-13-2014 07:07 AM
You can use the AXI Memory mapped or AXI stream options present in the FIFO generator core directly or the AXI steam fifo.
Check PG057 and PG080 for more details.
05-14-2014 11:56 PM
If you are looking from PS to PL through FIFO, the best option will be AXI stream FIFO.We already have had users use this.
Hope this helps . You can also also think of DMA solutions.
09-16-2015 03:08 AM
Even I have the same requirement
i went through the documents you mentioned but Im not getting how to design
did you find the solution for the requirement,if so please share the details
05-18-2018 09:03 AM
As I read it, the original poster wants a module with AXI on one side and native FIFO on the other side. The FIFO Generator can do either native or AXI, but can't mix them. Is there an easy solution to mixing them? Without it, I would need to maybe write an in-between-module that could convert between AXI-Stream and native FIFO signals, which are indeed very similar. I'd rather not have to write this, however. Any suggestions?
05-18-2018 09:34 AM
Have you looked at the axi4-stream fifo PG080?
It is axiLite or Axi4 to Axi stream. Axi stream interface is basically a fifo interface. For example, on axi4 to stream, VALID is basically fifo not empty, and READY represents fifo read.
05-18-2018 09:53 AM
Yes, I've looked at that. What you describe is exactly what I've already envisioned but would like to avoid doing -- building a middle module to convert AXI-Stream handshake to native FIFO handshake.
05-18-2018 11:09 AM
A simple method would be to use IPI HDL Modules. You would add an hdl file to your project that converts the signals, and then add it as a module to IPI. No need to repackage and create a new IP.
And if you don't want to use module flow, then I suggest to use IP packager to create a new IP and enable an AXI4 slave interface. I believe the example hdl generated for the core will infer a bram that you can read/write via AXI4. Then just modify that source to remove the bram inference and add your fifo interface.