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Newbie xdwumin
Newbie
1,873 Views
Registered: ‎03-05-2012

MapLib 979 978 error when create microblaze instance

After I create a Microblaze MCS in project navigator 13.4. 

 

The map is faild, error is:

 

NGDBUILD done.Process "Translate" completed successfully

Started : "Map".
Running map...
Command Line: map -intstyle ise -p xc4vlx40-ff668-10 -global_opt off -cm area -ir off -pr off -c 100 -o top_map.ncd top.ngd top.pcf
Using target part "4vlx40ff668-10".
Mapping design into LUTs...
ERROR:MapLib:979 - LUT4 symbol
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/RX_Frame_Error1" (output
   signal=vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/rx_frame_error) has input
   signal
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/new_rx_d
   ata<0>" which will be trimmed. See Section 5 of the Map Report File for
   details about why the input signal will become undriven.
ERROR:MapLib:979 - LUT4 symbol
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/new_rx_data_write_and00001" (output
   signal=vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/ne
   w_rx_data_write_and0000) has input signal
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/new_rx_d
   ata<0>" which will be trimmed. See Section 5 of the Map Report File for
   details about why the input signal will become undriven.
ERROR:MapLib:979 - LUT4 symbol
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/serial_to_parallel<1>1" (output
   signal=vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/se
   rial_to_parallel<1>) has input signal
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/new_rx_d
   ata<0>" which will be trimmed. See Section 5 of the Map Report File for
   details about why the input signal will become undriven.
ERROR:MapLib:979 - LUT3 symbol
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/start_Edge_Detected_0_and00001" (output
   signal=vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/st
   art_Edge_Detected_0_and0000) has input signal
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/previous
   _RX" which will be trimmed. See Section 5 of the Map Report File for details
   about why the input signal will become undriven.
ERROR:MapLib:979 - LUT3 symbol
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/start_Edge_Detected_0_and00001" (output
   signal=vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/st
   art_Edge_Detected_0_and0000) has input signal
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/new_rx_d
   ata<0>" which will be trimmed. See Section 5 of the Map Report File for
   details about why the input signal will become undriven.
ERROR:MapLib:979 - LUT2 symbol
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_TX.UART_TX_I1/tx_buffer_empty_i_or00001" (output
   signal=vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_TX.UART_TX_I1/tx
   _buffer_empty_i_or0000) has input signal "vor/vor_mcs/U0/LMB_Rst" which will
   be trimmed. See Section 5 of the Map Report File for details about why the
   input signal will become undriven.
ERROR:MapLib:978 - LUT4 symbol
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/RX_Frame_Error1" (output
   signal=vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/rx_frame_error) has an
   equation that uses input pin I1, which no longer has a connected signal.
   Please ensure that all the pins used in the equation for this LUT have
   signals that are not trimmed (see Section 5 of the Map Report File for
   details on which signals were trimmed).
ERROR:MapLib:978 - LUT4 symbol
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/new_rx_data_write_and00001" (output
   signal=vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/ne
   w_rx_data_write_and0000) has an equation that uses input pin I1, which no
   longer has a connected signal. Please ensure that all the pins used in the
   equation for this LUT have signals that are not trimmed (see Section 5 of the
   Map Report File for details on which signals were trimmed).
ERROR:MapLib:978 - LUT4 symbol
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/serial_to_parallel<1>1" (output
   signal=vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/se
   rial_to_parallel<1>) has an equation that uses input pin I2, which no longer
   has a connected signal. Please ensure that all the pins used in the equation
   for this LUT have signals that are not trimmed (see Section 5 of the Map
   Report File for details on which signals were trimmed).
ERROR:MapLib:978 - LUT3 symbol
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/start_Edge_Detected_0_and00001" (output
   signal=vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/st
   art_Edge_Detected_0_and0000) has an equation that uses input pin I0, which no
   longer has a connected signal. Please ensure that all the pins used in the
   equation for this LUT have signals that are not trimmed (see Section 5 of the
   Map Report File for details on which signals were trimmed).
ERROR:MapLib:978 - LUT3 symbol
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/start_Edge_Detected_0_and00001" (output
   signal=vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_RX.UART_RX_I1/st
   art_Edge_Detected_0_and0000) has an equation that uses input pin I1, which no
   longer has a connected signal. Please ensure that all the pins used in the
   equation for this LUT have signals that are not trimmed (see Section 5 of the
   Map Report File for details on which signals were trimmed).
ERROR:MapLib:978 - LUT2 symbol
   "vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_TX.UART_TX_I1/tx_buffer_empty_i_or00001" (output
   signal=vor/vor_mcs/U0/iomodule_0/IOModule_Core_I1/Using_UART_TX.UART_TX_I1/tx
   _buffer_empty_i_or0000) has an equation that uses input pin I0, which no
   longer has a connected signal. Please ensure that all the pins used in the
   equation for this LUT have signals that are not trimmed (see Section 5 of the
   Map Report File for details on which signals were trimmed).

Error found in mapping process, exiting...
Errors found during the mapping phase.  Please see map report file for more
details.  Output files will not be written.

Design Summary
--------------
Number of errors   :  12
Number of warnings :   0

Process "Map" failed

 

I only add a fixed timer and Uart in MCS, the module like this:

component mb_mcs is
  port (
    Clk : in STD_LOGIC := 'X'; 
    Reset : in STD_LOGIC := 'X'; 
    FIT1_Toggle : out STD_LOGIC; 
    UART_Rx : in STD_LOGIC := 'X'; 
    UART_Tx : out STD_LOGIC 
  );
end component;

 

the instance is:

 

vor_mcs	:	mb_mcs 
port map (
    Clk 						=>	clk50M,
    Reset 		=>	open,
    FIT1_Toggle 		=>	open,
    UART_Rx 		=>	open,
    UART_Tx			=>	mcs_uart_tx);

 

where clk50M is a 50MHz clock from top level module, and mcs_uart_tx is connected to an output bin in top level.

 

Any one know how to solve it?

 

Thanks

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