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Adventurer
Adventurer
3,937 Views
Registered: ‎11-10-2012

Memory Barrier Microblaze, Producer consumer problem

Hi,

I'd like to have an advice on this:

I have several µblazes implemented on a zynq platform. I have a program in DDR that is shared among the µblazes (so that any µblaze can execute any chunk of program, but never the same chunk of program can be executed by more than one µblaze at the same time). I&D caches are used for the execution.
On the other hand, i use the ARM to manage the number of µblazes running the program.
Any time i change the number of µblazes, each µblaze flush the cache so that the chunk of program being executed can be resumed by another µblaze.
So for instance, i can start the execution with 1 µblaze, then change to 16 µblazes and see the acceleration (the program is a video decoder) without stopping the system.
The problem appears when i change from 16 µblazes to 1. Since i call the "microblaze_flush_dcache" function, i suppose the entire cacheable range is flushed. So i suspect that some data that is updated in DDR by one µblaze, is being overwritten by the flushing of other µblaze's cache.

Do you think my suspicion is right?
If yes, is there a way to flush just the addresses that have been copied into the cache?

Notice that I suppose the cache's "write-back" has been completed (before resuming the execution with a new number of processors) using "mbar(0)" like pointed out here

 

http://forums.xilinx.com/t5/Embedded-Processor-System-Design/Memory-Barrier-Microblaze-Producer-consumer-problem/m-p/431548#M11215

 

Thanks in advance,

Yaset

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