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Scholar chevalier
Scholar
4,426 Views
Registered: ‎10-07-2011

Memory controller: Single wide port vs multiple narrow ports; Tradeoff

Hi folks,

 

No problem here. Just a chat. I'm not too familair with MPMC. The only one I know is that of the Spartan 6 (hardware MCB). It has 6 32-bit ports. Two of them are bidirectional while the other four are unidirectional. Multiple configurations can be achieved: single 128-bit RW, 2x 64-bit RW, 4x 32-bit RW, etc...

 

When building an embedded system including, let's say, a processor and a few other master devices sharing the same memory resource, we have the possibility to dedicate memory ports to a given master, or to connect everything through a single arbitrated bus.

 

Since the physical memory can only respond to one master at a time, I don't really see the benefit of having multiple ports. In my mind, a single wide port is better than 2 narrower ports or 4 even narrower ports. How can multiple narrow ports be preferable over a single wide port? The wider the port, the less clock cycles it takes to transfer a given number of bytes, hence the more time available to each master.

 

What would be the typical use case for multiple ports?

 

Thanks!

 

Claude

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5 Replies
Explorer
Explorer
4,425 Views
Registered: ‎08-12-2011

Re: Memory controller: Single wide port vs multiple narrow ports; Tradeoff

The multiple ports of the S6 memory controller are an advantage if you have multiple masters that need to access the memory - the multiplexing is done for you so you don't need to spend your time plus FPGA LUTs and FFs implementing the mux.

 

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Instructor
Instructor
4,420 Views
Registered: ‎07-21-2009

Re: Memory controller: Single wide port vs multiple narrow ports; Tradeoff

What would be the typical use case for multiple ports?

 

Example: Multiple processing engines (or datapaths) accessing shared data or storage.  This is a common usage case for signal processing.

 

Port 1:  Store acquired data

Port 2:  Fetching data, pre-scaling data, and storing data

Port 3:  Fetching data, filtering data, and storing data

Port 4:  Fetching data, rendering data, and displaying data

Port 5:  Embedded controller accessing data and stored variables for user interaction/display

 

Multiple ports means that each datapath can operate more independently, with overlapping accesses to memory, without additional buffering or interlocking "stall" logic.  In the example above:

  • Port 1 is "driven" by availability of acquired data.
  • Port 4 is "driven" by video display timing and frame rates

A single, wide data port can be a burden if datapaths are less wide, both for writing and reading.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Scholar chevalier
Scholar
4,408 Views
Registered: ‎10-07-2011

Re: Memory controller: Single wide port vs multiple narrow ports; Tradeoff

Hello eschabor,

 

Is there any benefit tieing a different master to each memory controller port rather than having a single (and faster) wide port connected to an arbitrated bus allocating time slots to each master devices?

 

In my application, I have 5 masters sharing access to the same DDR3 memory. My system is built in the EDK, around an AXI Interconnect (full AXI4). The S6 memory controller is attached to the AXI4 bus, as well as 5 master devices (a microblaze, a PCIe, and 3x AXI External Master Connectors interfacing custom VHDL modules).

 

The overall application needs very close to the full memory bandwidth. Hence, when a master needs to access the memory, it must release it as fast as possible because other masters are almost constantly waiting for the memory.

 

Would you say a multiple port approach could be beneficial in such a use case?

 

Thanks!

 

Claude

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Instructor
Instructor
4,406 Views
Registered: ‎07-21-2009

Re: Memory controller: Single wide port vs multiple narrow ports; Tradeoff

The overall application needs very close to the full memory bandwidth.

 

A general rule of thumb is that obtaining greater than 50% of the peak bandwidth on a sustained basis requires a concerted effort by the designer.

 

Here are some of the events which will result in sustained bandwidth which is less than 100% of peak bandwidth:

  • refresh
  • switching between read and write transactions (requires "dead" cycles on the DQ bus)
  • activate (open) an inactive row in a bank
  • de-activate (precharge) an active row

 

Managing the sequence of reads and writes and managing the address access patterns are both important aspects of maximising sustained effective memory bandwidth.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Explorer
Explorer
4,399 Views
Registered: ‎08-12-2011

Re: Memory controller: Single wide port vs multiple narrow ports; Tradeoff

Hi Claude,

 

As Bob has said, it's difficult to achieve anywhere near full memory bandwidth.  Without knowing details of the access patterns of your memory masters I don't know how multiple narrow ports would compare with one wide port.  I will say two things though:

 

* You can only get anywhere near full memory bandwidth if your memory accesses are of a good size.  "A good size" means at least the DDR3 transfer size of BL8, preferrably much larger.  Transfers of (say) 64 bytes and up should work well.

 

* A multi port controller can provide a significant advantage if it intelligently shares a DRAM between multiple masters.  An intelligent controller can perform clever tricks like reordering memory accesses to save bandwidth.  Tricks like write posting, write combining, selectively keeping pages open and overlapping activity across multiple banks can provide big wins, but they are all very dependent on the access patterns of the memory masters.

 

I don't know how clever the S6 MPMC is in this regard, I've never worked with it.  As you're working with XPS I recommend simply trying the easiest option first and seeing how it performs - if pointing and clicking in XPS can yield a working system with a five master AXI bus then by all means point and click, fire up your simulator and see how it performs.

 

-- 

Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au
$49 Spartan 6 board with 32MB DDR DRAM ?
http://www.sioi.com.au/shop/product_info.php/products_id/47

 

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