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Visitor kpados
Visitor
7,518 Views
Registered: ‎06-03-2014

MicroBlaze tutorial (UG940) adapted to AC701 eval board

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Hello,

 

I am following UG940 v2014.1 to get familiar with MicroBlaze. However, the evaluation board I have is an AC701, not the KC705 that the tutorial was originally written for. I have followed every step carefully, except for adding the "slave_banks" constraint that doesn't seem to apply 1:1 to the AC701.

 

The problem at hand is, when I get to step 11 (Executing the System) and I issue "connect mb mdm" in the XMD console, the JTAG chain is discovered successfully (also listing the CPU parameters and properties), but gives the following error message at the end:

 

ERROR: MicroBlaze is under RESET. Check if the Reset input to MicroBlaze and its Bus Interfaces are connected properly

UNABLE to STOP MicroBlaze

 

The reset on the board is high-active, which is consistent with the current setting of C_EXT_RESET_HIGH=1. Also, I tried executing the same command while I held the CPU_RESET switch of the board down which did not help, so I doubt the reset level is at fault here (at least not the reset level of the CPU).

 

Can you please provide some instructions to get the tutorial to work on the AC701 evaluation board?

 

Thank you

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Visitor michaelng
Visitor
9,739 Views
Registered: ‎07-14-2014

Re: MicroBlaze tutorial (UG940) adapted to AC701 eval board

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I was attempting to do the same thing (use UG940 for the AC701) and ran into the same problem. It appears that the MIG tool somehow sets the input clock to the wrong pins: N3/N2, which is designed to be a clock output to the DDR3. There will be nothing coming in on those pins, so the system never gets a clock and never comes out of reset.

 

The problem can be fixed by reconfiguring the MIG to use the correct clock input (SYSCLK on R3/P3). When I added clock ports and connected them, the tool complained, but it worked in the end.

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11 Replies
Xilinx Employee
Xilinx Employee
7,501 Views
Registered: ‎08-02-2007

Re: MicroBlaze tutorial (UG940) adapted to AC701 eval board

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Hi,

 

A quick check here would is to test the procedure outlined here.

 

http://www.xilinx.com/support/documentation/boards_and_kits/artix-7/ac701-bist-pdf-xtp194-2012.4-c.pdf

 

--Hem

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Visitor kpados
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7,472 Views
Registered: ‎06-03-2014

Re: MicroBlaze tutorial (UG940) adapted to AC701 eval board

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Thanks Hem, I've tried the BIST example as you suggested, and it works. However, I would still like to know why the steps detailed in the MicroBlaze tutorial fail for the AC701, to gain more knowledge and learn.

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Scholar sampatd
Scholar
7,466 Views
Registered: ‎09-05-2011

Re: MicroBlaze tutorial (UG940) adapted to AC701 eval board

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In step 11, instead of using the XMD console to program the fpga, can you try using Xilinx Tools> Program FPGA ?

Make sure that your bit file is updated with bootloop.elf
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Xilinx Employee
Xilinx Employee
7,464 Views
Registered: ‎08-02-2007

Re: MicroBlaze tutorial (UG940) adapted to AC701 eval board

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Hi,

 

Thanks for confirming BIST works. So Board and it's interface are working as expected :)

 

Let us do the following:-

 

1. Go to SDK GUI --> Xilinx Tools --> Launch EDK shell

2. Copy the download.bit, application.elf into one location

3. Type xmd at the console.

4. Type the command "fpga -f download.bit"

5. Type "connect mb mdm"

6. Type "dow application.elf"

 

If this works, then we might have to look at the SDK settings used.

 

--Hem

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Visitor kpados
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Registered: ‎06-03-2014

Re: MicroBlaze tutorial (UG940) adapted to AC701 eval board

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Thank you guys very much for your kind help.

 

@htsvn: Unfortunately, these steps don't work either. "dow application.elf" fails because the "connect mb mdm" command did not succeed.

 

@sampatd: I tried that too, but the result is the same even if I use the GUI to download the bitstream.

 

For reference, I have attached the XMD log to this post.

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Xilinx Employee
Xilinx Employee
7,418 Views
Registered: ‎08-02-2007

Re: MicroBlaze tutorial (UG940) adapted to AC701 eval board

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Hi

 

Quick thing to try, can you click on SW8(CPU reset) when trying to download the application?

 

--Hem

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Visitor kpados
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7,413 Views
Registered: ‎06-03-2014

Re: MicroBlaze tutorial (UG940) adapted to AC701 eval board

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Tried, no difference. But XMD doesn't even try downloading the application because it is not connected to the FPGA, since the connect-command failed.

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Visitor michaelng
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9,740 Views
Registered: ‎07-14-2014

Re: MicroBlaze tutorial (UG940) adapted to AC701 eval board

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I was attempting to do the same thing (use UG940 for the AC701) and ran into the same problem. It appears that the MIG tool somehow sets the input clock to the wrong pins: N3/N2, which is designed to be a clock output to the DDR3. There will be nothing coming in on those pins, so the system never gets a clock and never comes out of reset.

 

The problem can be fixed by reconfiguring the MIG to use the correct clock input (SYSCLK on R3/P3). When I added clock ports and connected them, the tool complained, but it worked in the end.

View solution in original post

Xilinx Employee
Xilinx Employee
7,093 Views
Registered: ‎08-02-2007

Re: MicroBlaze tutorial (UG940) adapted to AC701 eval board

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Hi,

 

That is a correct point. There is a known issue available here. (Xilinx Answer 60347) in the known issues of AC701.

 

The link seems to be broken. I will report this out to make it available

 

--Hem

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Explorer
Explorer
2,018 Views
Registered: ‎09-25-2014

Re: MicroBlaze tutorial (UG940) adapted to AC701 eval board

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Thanks you so much!

And is there is a way to get higher MB frequency with ac701 ?

Or 100 MHz is a limit there?

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Visitor _drakonoff
Visitor
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Registered: ‎10-17-2019

Re: MicroBlaze tutorial (UG940) adapted to AC701 eval board

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Hi =)

How did you disabled clk_ref port in MIG IP? I cannot search this option)

Vivado 2018.3

Thank you and best regards!

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