10-07-2011 07:57 PM
I'm working on a S6LX9 eval board from Avnet. Looking at the MHS file, I can see that M_AXI.IC and M_AXI_DC are tied to the same AXI4 bus. Onto that AXI4 bus, there is nothing else than 400MHz DDR3 memory (128MB I think). The M_AXI.DP is tied to an AXI4Lite bus loaded with a bunch of peripherals (Intc, Timer, GPIO, Ethernet, UART, SPI and so on; no memory). The M_AXI.IP is not connected. The I/DLMB are connected to 16KB BRAM. The Microblaze and buses are clocked at 67MHz.
1. It seems very weird to me to have 128MB CACHE when having only 16KB main memory (BRAM). I would expect the cache to be MUCH smaller than the main memory.
2. Can M_AXI.IC and M_AXI_DC be used for something else than CACHE?
3. In the MHS, the Microblaze parameters are sizing the I-Cache and D-Cache to 2K eack, even though they are connected to the entire 128MB. The address range for both caches is defined as the entire 128MB array.
4. Assuming everything is fine with the above, are we gaining something transfering data from 400MHz memory over a 67MHz AXI4 bus? Would it be better to use an AXI_BRAM_Controller along with BRAM for the cache?
10-10-2011 01:06 AM
1. You don't have 128 MB cache. You have 128 MB main memory. The cache size is determined in the MicroBlaze configuration, it can be anything from 128 bytes to 64kbyte. The LMB memory (16kb) is non-cached and have 0 latency.
2. Yes, MicroBlaze will do cacheline reads and writes on the M_AXI.IC and M_AXI.DC so only memory peripherals make sense like other external memory peripherals (Flash, SRAM,...).
4. Not sure I understand your question.
You want to move data from external memory to the AXI_M.DP interface?
I think you have misunderstood what is cache and what is memory.
In your system, you have a main memory (external DDR3) which is 128 MByte and a smaller local memory (LMB)
which is 16 kbyte. The main memory is accessed by MicroBlaze from it's caches which are 2kbyte each (Instruction
10-11-2011 09:00 AM
Thanks for the reply! That helped a lot but I still have a question. I read a lot of stuff about all that over the week-end. My confusion came from the impression that I had that the Microblaze C_ICACHE_BASEADDR and C_ICACHE_HIGHADDR parameters were defining the physical address of the actual cache memory, ie the 2KB cache memory itself. Now I understand that they define the CACHEABLE range, in my example the full DDR3 address space. I also now understand that the cache itself is not memory mapped.
What is still not clear to me, however, is whether I have to instanciate the cache memory myself or if it is part of the Microblaze core. For instance, it is clear that the LMB memory is something that I have to instanciate by myself, along with the needed BRAM controllers. But what about the cache. Do I have something to do?
08-03-2012 06:48 AM
i have some doubt regarding what you have discussed about.
In my system, i have 2GB DDR3 which i have connected to AXI4 using Microblaze IC & DC.
and also i have other memory mapped custome peripherals & external memoris like FLASH & SDRAM.
1. I had put 4KB as cache memory and 2GB (0x8000_0000 to 0xFFFF_FFFF) as cacheable address space and with this am able to access complete DDR3 memory.
2. Now when i connect FLASH and other memory mapped peripherals to the AXI4 IC & DC, i have to extend the microblaze's cacheable addr space right? so when i extend that to 3GB (0x4000_0000 to 0xFFFF_FFFF), am not able to access the peripherals which are connected in 0x4000_0000 to 0x7FFF_FFFF addr range and all AXI4 lite peripherals connected in (0x0000_0000 to 0x3FFF_FFFF) addr range.
What could be the reason?
can u give me some suggesion in this case about how do i connect other memory peripherals to microblaze IC & DC???
04-24-2018 12:46 AM
Hi @goran I've the same issue with VIVADO 2017.4.1, I've added into my Block Design the Microblaze with 32 KB local memory and 16 KB of Cache, to avoid all warning messages that tell me to add the Cache memory I've added a AXI EMC IP attached to the cellular memory on my board.