06-24-2009 10:04 AM
I am new to xilinx design tools and processes so please forgive my lack of knowledge.
I am trying to perform a timing analysis for read and write operations that occur over the FSL interface on the Microblaze. Using the XPS design tools I created a Microblaze-based system using the Base System Builder Wizard. I just followed a tutorial example for the BSB on the ML501 dev board. I created a "custom IP" using the IP import wizard and connected it through the FSL interface. I just used the example accumulator provided with the design tools. Using the example design code given for the software project I can see a read and write operation occur over the FSL Bus. So far, my understanding from the documentation is that it takes 2 clock cycles to place a 32-bit value from a register in the microblaze's register file unto the FIFO structure of the FSL Bus. How long does it take to read from the FIFO structure and place that value into a register? Is there a way to physically view this? Meaning, is there a way to view these operations as they occur on a wave form, or does microblaze have a timestamp register (rdtsc() equivalent instruction)? If I've left out anything please let me know. Any help or suggestions are greatly appreciated.
06-24-2009 10:34 AM
06-25-2009 08:01 AM - edited 06-25-2009 08:07 AM
I would recommend you to do a sw profiling. It's simple to do it using XMD, which you can launch in EDK. Be aware to set memory space for the profiling. The result will show you how much time a sw funnction takes to run in seconds. It is based on gprof utility.Take a look at http://ecee.colorado.edu/~ecen4633/LAB/edk_prof.pdf
You can also use EDK-SDK instead if you want, instead of XPS.
This should do what you want.