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Adventurer
Adventurer
2,971 Views
Registered: ‎03-16-2010

Microblaze does not use write bursts

I am using XPS 13.4 with a Microblaze 8.20a connected via AXI to a custom peripheral which is connected to the DDR.

 

+------------------+    +-----+    +------------------+    +-----+

| uBlaze           | => | AXI | => | My IP            | => | DDR |

| D$:              |    |     |    | From: 0x40000000 |    |     |

| From: 0x40000000 |    |     |    | To:   0x5FFFFFFF |    |     |

| To:   0x4FFFFFFF |    |     |    |                  |    |     |

+------------------+    +-----+    +------------------+    +-----+

 

The Microblaze is configured with a writeback cache to enable write bursts. All AXI ports on the Microblaze are connected to My IP. The cachable address range is half of the range assigned to My IP (e.g.: the first half is cached, the second half is uncached).

 

When using XMD the data cache is enabled and a read on the cached range is performed. This results in an 8 word read burst. Then some words are written into the range that was just loaded to make the cache line dirty.

 

When a read is performed from an address 0x1000 further in the memory range, the cache needs to be flushed.

 

However, the cache flush is done over the AXI DP port instead of the AXI DC port in 8 separate writes instead of a single burst.

 

Like I said, the write back cache is enabled and the MPD has "ADDR_TYPE = MEMORY, CACHEABLE = TRUE" on the BASEADDR parameter. What else is needed to enable write bursts on the Microblaze 8.20a using AXI?

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Adventurer
Adventurer
2,920 Views
Registered: ‎03-16-2010

Re: Microblaze does not use write bursts

I still have this issue.

 

This is part of my MHS file:

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_mb0
 PARAMETER HW_VER = 8.20.b
 PARAMETER C_FAMILY = virtex6
 PARAMETER C_PVR = 1
 PARAMETER C_PVR_USER1 = 0x00
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_INTERRUPT_IS_EDGE = 1
 PARAMETER C_ICACHE_LINE_LEN = 8
 PARAMETER C_ICACHE_BASEADDR = 0x40000000
 PARAMETER C_ICACHE_HIGHADDR = 0x43FFFFFF
 PARAMETER C_DCACHE_LINE_LEN = 8
 PARAMETER C_DCACHE_BASEADDR = 0x40000000
 PARAMETER C_DCACHE_USE_WRITEBACK = 1
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_MSR_INSTR = 1
 PARAMETER C_USE_PCMP_INSTR = 1
 PARAMETER C_ILL_OPCODE_EXCEPTION = 1
 PARAMETER C_ICACHE_STREAMS = 1
 PARAMETER C_USE_BRANCH_TARGET_CACHE = 1
 PARAMETER C_BRANCH_TARGET_CACHE_SIZE = 2
 PARAMETER C_CACHE_BYTE_SIZE = 32768
 PARAMETER C_DCACHE_BYTE_SIZE = 32768
 PARAMETER C_DCACHE_VICTIMS = 8
 PARAMETER C_ICACHE_VICTIMS = 8
 PARAMETER C_USE_DIV = 1
 PARAMETER C_USE_HW_MUL = 2
 PARAMETER C_USE_FPU = 2
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_DCACHE_HIGHADDR = 0x4FFFFFFF
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_USE_DCACHE = 1
 BUS_INTERFACE M_AXI_DP = axi_mb0
 BUS_INTERFACE M_AXI_IP = axi_mb0
 BUS_INTERFACE DLMB = lmb_dmem_mb0
 BUS_INTERFACE ILMB = lmb_imem_mb0
 BUS_INTERFACE M_AXI_DC = axi_mb0
 BUS_INTERFACE M_AXI_IC = axi_mb0
 BUS_INTERFACE DEBUG = mdm_mb0
 PORT MB_RESET = rst_core
 PORT INTERRUPT = timer_interrupt_mb0
END

 

BEGIN interconnect
 PARAMETER INSTANCE = interconnect_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_FAMILY = virtex6
 PARAMETER C_mb0_BUS_S_AXI_BASEADDR = 0x40000000
 PARAMETER C_mb0_BUS_S_AXI_HIGHADDR = 0x5FFFFFFF
 PARAMETER C_INTERCONNECT_MB0_BUS_S_AXI_MASTERS = microblaze_mb0.M_AXI_DP & microblaze_mb0.M_AXI_IP & microblaze_mb0.M_AXI_DC & microblaze_mb0.M_AXI_IC
 PORT rst = rst_ip
 PORT clk = clk
 PORT mb0_BUS_S_AXI_ACLK = clk
END

 

Note that the standard name S_AXI is not used here. The reason is that this is a simple example, the complete version is used to interconnect multiple CPUs to the DDR.

 

This is the description of the 'interconnect' IP from the MPD:

BEGIN interconnect
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION DESC = INTERCONNECT
OPTION STYLE = MIX
PARAMETER C_FAMILY = virtex5, DT = STRING

## Bus Interfaces
BUS_INTERFACE BUS = MB0_BUS_S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE

## Generics for VHDL
# Parameters for MB0_BUS_S_AXI
PARAMETER C_MB0_BUS_S_AXI_PROTOCOL = AXI4, DT = STRING, BUS = MB0_BUS_S_AXI, ASSIGNMENT = CONSTANT, TYPE = NON_HDL
PARAMETER C_MB0_BUS_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = MB0_BUS_S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_MB0_BUS_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = MB0_BUS_S_AXI, RANGE = (32, 64, 128, 256, 512, 1024)
PARAMETER C_MB0_BUS_S_AXI_BASEADDR = 0xffffffff, DT = std_logic_vector(31 downto 0), PAIR = C_MB0_BUS_S_AXI_HIGHADDR, ADDRESS = BASE, BUS = MB0_BUS_S_AXI, ADDR_TYPE = MEMORY, CACHEABLE = TRUE, MIN_SIZE = 0x1000, ASSIGNMENT = REQUIRE, TYPE = NON_HDL
PARAMETER C_MB0_BUS_S_AXI_HIGHADDR = 0x00000000, DT = std_logic_vector(31 downto 0), PAIR = C_MB0_BUS_S_AXI_BASEADDR, ADDRESS = HIGH, BUS = MB0_BUS_S_AXI, CACHEABLE = TRUE, ASSIGNMENT = REQUIRE, TYPE = NON_HDL
PARAMETER C_MB0_BUS_S_AXI_ID_WIDTH = 1, DT = INTEGER, BUS = MB0_BUS_S_AXI
PARAMETER C_MB0_BUS_S_AXI_SUPPORTS_NARROW_BURST = 0, DT = INTEGER, TYPE = NON_HDL, BUS = MB0_BUS_S_AXI, ASSIGNMENT = CONSTANT

## Ports
# Ports for MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_ARREADY = ARREADY, DIR = O, BUS = MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_ARVALID = ARVALID, DIR = I, BUS = MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_MB0_BUS_S_AXI_ADDR_WIDTH-1):0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_ARLEN = ARLEN, DIR = I, VEC = [7:0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_ARSIZE = ARSIZE, DIR = I, VEC = [2:0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_ARBURST = ARBURST, DIR = I, VEC = [1:0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_ARPROT = ARPROT, DIR = I, VEC = [2:0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_ARCACHE = ARCACHE, DIR = I, VEC = [3:0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_ARID = ARID, DIR = I, VEC = [(C_MB0_BUS_S_AXI_ID_WIDTH-1):0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_ARLOCK = ARLOCK, DIR = I, BUS = MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_RREADY = RREADY, DIR = I, BUS = MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_RVALID = RVALID, DIR = O, BUS = MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_MB0_BUS_S_AXI_DATA_WIDTH-1):0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_RLAST = RLAST, DIR = O, BUS = MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_RID = RID, DIR = O, VEC = [(C_MB0_BUS_S_AXI_ID_WIDTH-1):0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_AWREADY = AWREADY, DIR = O, BUS = MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_AWVALID = AWVALID, DIR = I, BUS = MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_MB0_BUS_S_AXI_ADDR_WIDTH-1):0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_AWLEN = AWLEN, DIR = I, VEC = [7:0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_AWSIZE = AWSIZE, DIR = I, VEC = [2:0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_AWBURST = AWBURST, DIR = I, VEC = [1:0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_AWPROT = AWPROT, DIR = I, VEC = [2:0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_AWCACHE = AWCACHE, DIR = I, VEC = [3:0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_AWID = AWID, DIR = I, VEC = [(C_MB0_BUS_S_AXI_ID_WIDTH-1):0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_AWLOCK = AWLOCK, DIR = I, BUS = MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_WREADY = WREADY, DIR = O, BUS = MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_WVALID = WVALID, DIR = I, BUS = MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_MB0_BUS_S_AXI_DATA_WIDTH-1):0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_MB0_BUS_S_AXI_ADDR_WIDTH/8)-1):0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_WLAST = WLAST, DIR = I, BUS = MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_BREADY = BREADY, DIR = I, BUS = MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_BVALID = BVALID, DIR = O, BUS = MB0_BUS_S_AXI
PORT MB0_BUS_S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
PORT MB0_BUS_S_AXI_BID = BID, DIR = O, VEC = [(C_MB0_BUS_S_AXI_ID_WIDTH-1):0], BUS = MB0_BUS_S_AXI, ENDIAN = LITTLE
# Top-level Ports
PORT rst = "", DIR = I
PORT clk = "", DIR = I
END

Right now we are not using C_DCACHE_ALWAYS_USED to force the use of the Data Cache port. But when enabling the data read results in burst reads over DC it seems not too far of a stretch that at that point write bursts are also performed using DC. Instead we still see eight separate writes over DP.

What is going wrong here?

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