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Observer davidsummers
Observer
2,102 Views
Registered: ‎05-18-2015

Microblaze fault tolerance ECC slow performance

I have a Virtex 5 Design using ISE 13.2 with a Microblaze processor.   My clock rate is 60Mhz.  When I enable the fault tolerance features of the microblaze, the LMB_BRAM ECC logic becomes the critical path and the design fails to meet timing at 60Mhz.

 

The Virtex 5 BRAMs have built in hard ECC logic, but the microblaze BRAMS are not using the hard ECC, but are instead implementing ECC using fabric slices.

 

Is there any way to force the LBM_BRAM controllers to use the built in BRAM ECC instead of using fabric resources?

 

Is there any advice on improving the timing of the LMB_BRAM ECC?

 

 

I have attached a screenshot of the timing report on one of the failing paths



Microblaze_ECC_Timing.PNG
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Xilinx Employee
Xilinx Employee
1,931 Views
Registered: ‎08-06-2007

Re: Microblaze fault tolerance ECC slow performance

Hi,

 

Unfortunately so doesn't the hard ECC work with MicroBlaze due to two reasons.

1. The hard ECC only works for 64-bit data wide and MicroBlaze are using 32-bit

2. The hard ECC doesn't work for dual-port mode which is essential for MicroBlaze shared instruction and data memory.

 

You could try with some area constraints on the BRAM and MicroBlaze and see if this reduced the routing delays.

 

Göran

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