12-21-2018 01:20 AM
I am new to Microblaze.
I have run some sample code on AC701, Vivado 2016.2 using microblaze subsystem (axi uart lite, Axi GPIO, Axi xadc) etc.
No I would like to interface microblaze subsystem to FPGA fabric. My intention is to use Microblaze subsystem as a part of my HDL design.
How to do this ?? is there any documentation or example implementation for this design.
I requirements is to
1. generate interrupts to microblaze subsystem
2. GPIO signalling b/w Microflaze and FPGA hDL
3. Register access... Shared register between microBlaze and FPGA HDL.... used to pass parameters to miroblaze and vice versa
Is there any example design for the above??
12-21-2018 02:15 AM
It's probably important to understand that the Microblaze is part of the FPGA fabric (it is not a hard processor like the ARM in a SoC) and, as such, you can simply consider it to be a module just like any other VHDL module.
At a subsystem level, the Microblaze is usually instantiated with some AXI structure and probably an interrupt aggregator plus local BRAM. I can't really think why you would connect a GPIO module to another custom module when you could simply do an AXI transfer to the custom module UNLESS you don't want to place an AXI slave front end to your (presumably already extant) custom module.
Interrupt handling is just routing a signal from your custom module to the interrupt module (I assume AXI based), taking note of signal polarity and whether or not that signal is edge or level sensitive, as defined by the interrupt handling module (there may need to be signal attributes applied to allow you to connect the two together in Vivado block design .. I'm not sure).
I don't have a great deal of experience with Vivado but I have handled Microblaze in ISE. I expect that you would like to do all of this at a Block Design level (and, subsequently, will/have generate a block for your custom modules)?
I would have thought that it is fairly easy to take your sample project and add in your custom IP. I'm going to create an example project to do just this and see if I can help you further, on the fly.
12-21-2018 04:08 AM
Which are the AXI modules that need to to included to have AXI transfer for signalling than using traditional signals??...
Is this a Dual port ram module or something else??
12-21-2018 04:36 AM
Here's a Microblaze subsystem, in Block Design, based on the AC701 development board included in Vivado (I'm using 2016.4).
You can see the microblaze_0_axi_periph component which is effectively interconnect between the Microblaze (as Master) and the other submodules (as Slaves). See how it connects to the GPIO and the UART. I've added in an interrupt controller, too, which connects to the Microblaze interrupt port (although I haven't connected an input to it yet - one could connect the UART interrupt signal to the interrupt controller, for example).
From the IP catalogue, there are literally hundreds of IP that you can add - you can have a DPRAM if you want. When you add some IP, Vivado is smart enough to do Block Automation and connect it up for you, if you select it. So any AXI interface IP will be automatically connected to the AXI peripheral and will be memory mapped to the Master (e.g. the Microblaze).
My plan for this example (learning exercise for myself, actually) is to create and add some custom IP and connect it to the AXI peripheral, then output an interrupt to the interrupt controller). I haven't generated any software for this system but it should give you an idea of how to proceed.
12-23-2018 08:21 PM
So as I understand AXI access will be easier from Microblaze... but from HDL i will have to handcode each and every AXI access ...
12-24-2018 12:16 AM
What do you mean "handcode each and every access"? You will have to decode the accesses inside the memory mapped area.
You can use the tools to create an AXI4 peripheral and place your custom IP under that.