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Observer loyalluna
Observer
7,435 Views
Registered: ‎07-13-2015

Multiple DRAM access by ACP

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Hi everyone,

I want to have multiple parallel access to DRAM from PL section, is it acheivable?
I need the data to be coherent, means that I should use ACP port.
I did read and write through different HP ports once, means I could read and write at the same time from different ports. However, I do not know the ACP port has this ability to accept read and wtite in parallel from just one interface?
to use ACP port I use an AXI interconnect to connect many Masters to it and then connect the interconnect to the ACP prot. does it make sense?


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Xilinx Employee
Xilinx Employee
14,195 Views
Registered: ‎07-30-2007

Re: Multiple DRAM access by ACP

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No. Zynq ACP has a total ID width of 3.

You can have a single master of 3 ID bits. Or up 8 masters without IDs going through an AXI Interconnect. Or up to 4 masters who each have 1 ID bit of their own. All of which add up to 3 bits of total ID width.

Or in theory you can write your own core with stores/removes/reflects the ID and have as many masters as you want.
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Xilinx Employee
Xilinx Employee
7,424 Views
Registered: ‎07-30-2007

Re: Multiple DRAM access by ACP

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Yes, you can use an AXI Interconnect to share a single ACP interface for coherence- just add the Interconnect IP, connect up the clocks, and make sure the ACP CACHE and USER signaling is handled.

 

Good luck!

Dylan

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Observer loyalluna
Observer
7,409 Views
Registered: ‎07-13-2015

Re: Multiple DRAM access by ACP

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@dylan
So I used interconnect and was successfull while I used just three AXI MASTER.
when I added the forth one I received this message:


[BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /processing_system7_0/S_AXI_ACP(5) and /axi_interconnect_1/m00_couplers/auto_pc/M_AXI(0)

I used two interconnect to solve it but no success.

AXI Masters I used are 64bits and 32 bits which have different burst length.

Any suggestion?

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Observer loyalluna
Observer
7,406 Views
Registered: ‎07-13-2015

Re: Multiple DRAM access by ACP

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When I add the forth AXI Master I received this :
[BD 41-237] Bus Interface property ID_WIDTH does not match between /processing_system7_0/S_AXI_ACP(3) and /axi_mem_intercon/m00_couplers/auto_pc/M_AXI(4)

and the previous one was when I used two different Master AXI s
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Xilinx Employee
Xilinx Employee
7,399 Views
Registered: ‎07-30-2007

Re: Multiple DRAM access by ACP

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The ACP interface is up to 3 bits wide of AXI ID. To have 4 masters, you would have a minimum of 2 bits of ID. To have 4 bits of ID, you must have a master which has at least two bits of ID on the master itself, or are perhaps cascading interconnects.

 

In other words, the total ID width is the widest ID width on a master, plus log2 of the number of masters.

 

 

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Observer loyalluna
Observer
7,397 Views
Registered: ‎07-13-2015

Re: Multiple DRAM access by ACP

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 @dylan So, the ACP interface can accept totally 4 Master AXI ?

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Xilinx Employee
Xilinx Employee
14,196 Views
Registered: ‎07-30-2007

Re: Multiple DRAM access by ACP

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No. Zynq ACP has a total ID width of 3.

You can have a single master of 3 ID bits. Or up 8 masters without IDs going through an AXI Interconnect. Or up to 4 masters who each have 1 ID bit of their own. All of which add up to 3 bits of total ID width.

Or in theory you can write your own core with stores/removes/reflects the ID and have as many masters as you want.
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Observer loyalluna
Observer
7,381 Views
Registered: ‎07-13-2015

Re: Multiple DRAM access by ACP

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Thanks
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