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Visitor new_student
Visitor
5,729 Views
Registered: ‎05-19-2016

OSERDES2 simulation - no output

Hi,

I'm currently working with the OSERDES of a Zynq. If I'm using the SelectIO wizard, everything works fine.

But for my current project I need to use the OSERDES2 directly in my VHDL files. So I used the templates and the reference design files from XAPP585. But if I try to run my testbench, the outputs stay in state 'X' all the time.

Since the clocks and the reset work as expected during simulation, I think I made a mistake with the OSERDES2.

 

May you pleas have a look at the attached VHDL file, please?

 

 

Best regards

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1 Reply
Visitor new_student
Visitor
5,690 Views
Registered: ‎05-19-2016

Re: OSERDES2 simulation - no output

Hi,

 

it seems like I found the Problem. If I assign the clock after some ns it works almost like expected.

Except that the serialised data is not in sync with CLKDIV. So I made a project with a minimalistic block design, including a clocking wizard and the selectIO core. Serialisation is set to SDR with a factor of 8. The DIVCLK is forwarded as well. CLK is set to 800MHz and CLKDIV to 100MHz; both via the clocking wizard.

 

Running the simulation results in a strange behavior. The clock is forwarded correctly and the data is serialised but the data is not in sync with the forwarded clock (CLKDIV)?

 

What am I missing here?

 

Attached you will find the minimalistic design.

 

Best regards.

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