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Registered: ‎12-26-2016

PL DMA asserts tvalid too soon - false data transmitted

Hi there,

I have a Xilinx DMA connected to a ZynqHP0 port and want to transmit data from DDR into PL. The data is generated by a firmware on the PS and stored in a reserved memory space in the DDR region. On the A9 processors a PetaLinux is running. I use the Vivado 2018.2 toolchain.

To ensure I transfer the correct data to my system I use an ILA in the PL probing the AXIL config port and AXIS interface port of the DMA running in normal operation. According to devmem and my settings the first transferred data should be decimal 131071/1. Then 63 zeros and 131071/2, 63 zeros, 131071/3, 64 zeros .... in total 8192 bytes on the MM2S interface should be transferred.

Looking at the waveforms of the ILA I see the first tvalid assertion but no valid filter_tdata. The valid datastream starts at the second rising edge of tvalid.

ILA.pngPink marks false data transmitted

Looking at devmem output of the PetaLinux shows valid data at 0x0a000000

root@petalinux:~# devmem 0x0a000000 32 
root@petalinux:~# devmem 0x0a000004 32 
root@petalinux:~# devmem 0x0a000008 32 

We had some problems with our DDR configuration with a MT41K256M16TW-107 memory so we use the MT41J256M RE-125 preset on a custom board.

How does the DDR controller affect the PL DMA? Seeing the whole DDR transaction as a black-box I would expect valid data on tdata when tvalid is high. Are there any trapdoors hidden?

If you need further information don't hesistate to ask :)


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2 Replies
Registered: ‎12-26-2016

Re: PL DMA asserts tvalid too soon - false data transmitted

I just flashed the same thing on the DevKit we use and there is the same problem.
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Xilinx Employee
Xilinx Employee
Registered: ‎10-04-2016

Re: PL DMA asserts tvalid too soon - false data transmitted

Hi @tmaintz ,

I don't think your ILA waveform doesn't show what you think it does.

The wdata you are pointing at appears to belongs to the AXI-Lite interface of the AXI DMA. The AXI-Lite interface is the control interface for the IP. The wdata 0x2000 is the number of bytes you intend to transfer and is an artifact of writing to register 0x28 (the MM2S_LENGTH register).

To see the data coming out of the stream side of the MM2S channel, you should have a signal with the name _tdata. It is part of the M_AXIS_MM2S interface.

To see the data read from 0xA000_0000 on the memory mapped side of the MM2S channel, you would need to instrument the M_AXI_MM2S read address and read channels.




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