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Adventurer
Adventurer
646 Views
Registered: ‎10-12-2018

PL-PS AXI Burst

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Hello to all,

I have designed an AXI master interface IP to read data from a specific bus (a standard bus in our company) and transfer the data through one of the HP ports to the DDR memory in PS part. The data width of our bus is either 64 or 128 bits and because of that, I set the AXI4 data width to 128 bits. And for having the highest throughput, I have set the burst length to 256.

In the case of 128bit data width, everything goes fine since every beat of a burst has enough data to transfer; And the data will be stored continuously in the memory. But for 64 bits, half of a beat would be unused. Because of that, I am ignoring one beat by putting the write strobes bits to 0, and instead of that, the two 64bit are concatenated to make a 128bits beat. In other words, every other beat is an empty beat. That means in the DDR memory, the data will not be continuous because of the empty beats. There would be a chain of 128bit data and 128bit gap continuously.  

Is there any way to solve this problem in AXI burst process? For example, ignore address increment on every beat? ;)

Thank you very much. Looking forward to hearing from you.

Kindest regards,

Amir

 

 

 

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1 Solution

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Voyager
Voyager
582 Views
Registered: ‎02-01-2013

Re: PL-PS AXI Burst

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It sounds like you have hopes that WSTRB can be handled like TKEEP--from AXI Stream. i.e, You want some AXI structure that is able to compact the data in your transfer into a smaller organization for you, by nudging valid bytes 'ahead' into positions that contained invalid bytes. 

Unfortunately, WSTRB is not the same as TKEEP.  TKEEP is a "byte valid" signal in a stream of data, where actual position is irrelevant and only relational position matters. Invalid bytes there can be dropped, thereby compacting the stream.

WSTRBs, on the other hand, represent precise, positional bytes. One of their main uses is as a write-enable flag, so only targeted bytes within a transfer actually get written, while the others are ignored.

There are only 3 types of bursts in AXI: Fixed, Incr, and Wrap. Fixed and Wrap are not helpful for transfers to DDR. That leaves only the Incr burst you're already using. From the AXI spec: "In an incrementing burst, the address for each transfer in the burst is an increment of the address for the previous transfer. The increment value depends on the size of the transfer."

The only was I can see doing what you want is by sending the data (when it's 64 bits wide instead of 128) out a separate 64-bit AXI interface. So your IP would need 2 master AXI interfaces: 1 with 64-bit write data and 1 with 128-bit data. The 64-bit interface would go through an AXI interconnect, of sorts, before being injected into the targeted 128-bit AXI port of the PS. But to support bursting during the data-width translation, that AXI interconnect is going to need buffering--which means it's going to need the same as the FIFO you say you don't want to waste PL memory resources on.

-Joe G.

 

4 Replies
Voyager
Voyager
614 Views
Registered: ‎02-01-2013

Re: PL-PS AXI Burst

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Your problem seems to be fixable at the source. If it were me, I'd pack the arriving 64-bit data into a 128-bit-wide FIFO. Depending on the arrival/departure clock-ratio, I'd start sending 128-bit data to the PS when the FIFO hit a particular threshold. Every strobe of the outgoing AXI burst would be set--except perhaps the last, it there were an odd number of 64-bit words for some reason--and throughput would be maximized.

There might be an AXI module that could squeeze-out unused bytes, but since you already know the expected data-gap pattern, the best course would be to handle it in your initial module.

-Joe G.

 

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Adventurer
Adventurer
602 Views
Registered: ‎10-12-2018

Re: PL-PS AXI Burst

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@jg_bds Thank you for the reply.

I know it can be managed by packing the data into 128-bit-wide FIFO, and then sending. It would be my last solution, and I prefer to not use memory as much as possible.

Any other idea?

Sincerely yours,

Amir

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Voyager
Voyager
583 Views
Registered: ‎02-01-2013

Re: PL-PS AXI Burst

Jump to solution

It sounds like you have hopes that WSTRB can be handled like TKEEP--from AXI Stream. i.e, You want some AXI structure that is able to compact the data in your transfer into a smaller organization for you, by nudging valid bytes 'ahead' into positions that contained invalid bytes. 

Unfortunately, WSTRB is not the same as TKEEP.  TKEEP is a "byte valid" signal in a stream of data, where actual position is irrelevant and only relational position matters. Invalid bytes there can be dropped, thereby compacting the stream.

WSTRBs, on the other hand, represent precise, positional bytes. One of their main uses is as a write-enable flag, so only targeted bytes within a transfer actually get written, while the others are ignored.

There are only 3 types of bursts in AXI: Fixed, Incr, and Wrap. Fixed and Wrap are not helpful for transfers to DDR. That leaves only the Incr burst you're already using. From the AXI spec: "In an incrementing burst, the address for each transfer in the burst is an increment of the address for the previous transfer. The increment value depends on the size of the transfer."

The only was I can see doing what you want is by sending the data (when it's 64 bits wide instead of 128) out a separate 64-bit AXI interface. So your IP would need 2 master AXI interfaces: 1 with 64-bit write data and 1 with 128-bit data. The 64-bit interface would go through an AXI interconnect, of sorts, before being injected into the targeted 128-bit AXI port of the PS. But to support bursting during the data-width translation, that AXI interconnect is going to need buffering--which means it's going to need the same as the FIFO you say you don't want to waste PL memory resources on.

-Joe G.

 

Adventurer
Adventurer
531 Views
Registered: ‎10-12-2018

Re: PL-PS AXI Burst

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@jg_bds

Thank you for your explanations.

You are right, sending out the data through two separate interfaces is the only solution. 

Regards,

Amir

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