PL access to PS MIO pins

[geoffbarnes]

Looking into the MIO pins on the Zynq.   We can have PS periphs access MIO pins (top-left pic), or optionally go to the PL via EMIO (top-right).   However, it's not clear to me if we can configure things such that the PL controls selective PS_MIO pins as in the bottom pic?    This would be useful when you might want to implement custom logic on an existing board.

Thanks..

[austin]

g,

Note the arrowheads, and which way they point.

[geoffbarnes]

Still don't get it... any other hints?  

[austin · Accepted solution]

I really doubt you can connect to the MIO pins through the PL,

It is hard to imagine what the use case is....

So, I don't know.  But from what I've read, I don't think so...

[muzaffer]

>> Note the arrowheads, and which way they point.

all the arrowheads point both ways ie arrows up & down and left & right which suggests reading PS IO from PL is possible but probably not possible in reality?

[geoffbarnes]

Use case is probably rare..

Had a situation in the past where some tuning and amplifier circuitry were controlled by sw via SPI.   A new unforseen appllication came up requiring these to be controlled hard real-time.   Since the SPI bus was hanging off the FPGA, the fix was simple.

Also had situations where the FPGA was used to workaround proprietary protocol extentions, fix bugs in 3rd party devices, etc.

There's probably a small loss of flexibility in using MIO in some cases.

[larthe]

Hi all!

I disagree that the use cases would be rare. One obvious would be if (when) you run out of pins in the SelectIO of the PL. It would have been great if you could resort to a few left-over MIO pins in that case.

And of course the case already mentioned above, to work around errors on an existing board.

But it seems pretty clear now that you can't, even though the arrow heads go both ways in the illustration Austin.... (Unless this is wrong and someone with deeper knowledge steps in and sets us straight!)

/Lars

[daleye]

Not trying to cross post, but AR# 61861 also details a use case. 

I have an I2C periperhal tied directly to MIO pins. Since there is no filtering, glitches cause the program to halt. This was replicated and resolved on an ZC706 where the I2C could be brought out to PL pins through the EMIO function. Putting the aforementioned AR filter block in between the PS I2C and the I2C Peripheral eliminated the program crash.

Now how do put this filtering in place between the peripheral and the ARM if I can't shoehorn some logic between?

[trenz-al]

there are more use cases, and yes the "PL to MIO" mux could have helped to fix the I2C filter issue.

[olupj]

I have another use case...

Having a Zedboard, want to develop and test custom controller core in fabric, develop driver against the processor.

That would be convenient.  Ultimately, in product, this isn't a valid use case, but good for development.

Solution: get PMOD -SD cardslot converter.

Not too bad.

Just FYI as another solution / case...

Regards,

~Jerry

[daniel.kho]

Me too. I have another use case where the dev board I have routed PS MIO pins to some external interface connectors or chips (e.g. gigabit ethernet or USB) but I really want to access those interfaces directly from the PL. I rather not write additional software just to be able to talk to those interfaces... -dan

[truptic91]

Hi,

I am working on xc7z100ffg900 in Vivado 2016.4

I want to access signals coming on MIO pins in PS into the PL through EMIO.

In my UART application, one signal is RX coming from external world on MIO pin(MIO22). MIO pin -> EMIO ->PL

similarly, another signal TX coming from PL goes to external world through MIO pin(MIO23). PL->EMIO->MIO pin

I have my own code for UART, which will be implemented in PL. I just need rx/tx interfacing signals in PL from above mentioned MIO pins.

How to configure above for my application in ZYNQ7 processing system IP?

Thanks in advance.

[muzaffer]

@truptic91 what you want can't be done. ie you can't read/drive MIO pins from PL implementation. Only the reverse ie controlling PL IO pins through PS blocks is possible