05-16-2019 11:04 AM - edited 05-16-2019 11:06 AM
I am trying to load the PL portion of my design through FPGA manager, which for the moment is a test design with only a few gpios and a ddr4 memory ip core. My project compiles and I've generated the bitstream, and am able to do some standard LED blinks through a baremetal driver through the SDK.
Now I wanted to load the PS onto a linux system and try using FPGA manager to load the PL afterwords. I followed the main steps, petalinux-create -> petalinux-config with my .hdf file and fpga manager selected, as well as petalinux-build and petalinux-package.
After this, I put my BOOT.bin and image.ub on an SD card and am able to boot my file system and kernel.
Now, when I want to load the PL, I do an scp of the .bit.bin and the .dtbo files that petalinux generated for my project, namely, the files in
/project_dir/build/tmp/sysroots-components/zcu111_zynqmp/fpga-manager-util/lib/firmware/base/design.bit.bin, and base.dtbo
Now that I have it on my machine, I try a fpgautil -b design_1_wrapper.bit.bin -o base.dtbo , and get the following message through the console:
root@xilinx-zcu111-2018_3:~/temp_files# fpgautil -b design_1_wrapper.bit.bin -o base.dtbo
[ 427.020618] fpga_manager fpga0: writing design_1_wrapper.bit.bin to Xilinx ZynqMP FPGA Manag
[ 427.275452] zynqmp_clk_divider_set_rate() set divider failed for pl0_ref_div1, ret = -13
Time taken to load DTBO is 266.000000 Milli Seconds
DTBO loaded through zynqMP FPGA manager successfully
I receive this message regardless of trying another projects hardware files, also created through the petalinux interface (I'm using petalinux 2018.3).
Does anyone have any idea as to why this is? I can also provide my hardware design if needed, but it is not much more than a ZynqMP+, ddr4, a bram and a few gpios.
05-17-2019 04:27 AM
This flow is covered here:
If your use case is to not have the PL bitstream in the BOOT.BIN (ie if booting over tftp for example), then you can do the following:
Creating Image in Petalinux 2018.3:
I have a helper script that you can use (attached here)
Creating BIN, and DTO:
Launch XSCT, and source the attached helper script. Run the commands below:
Testing on Hardware:
Place the BOOT.BIN, image.ub, design_1_wrapper.bit.bin, pl.dtbo onto an SD card and boot:
Use the commands on the wiki to test:
05-17-2019 06:41 AM
Thank you for your response, however, I noticed you also received the zynqmp_clk_divider_set_rate() set divider failed for pl0_ref_div1, ret = -13 error as I did.
This seems to affect how the clock works for certain IPs such as the GPIO.
05-20-2019 03:12 PM
05-29-2019 07:25 AM
Did you end up figuring out the reason for this?
I also ran into the same thing using fpgautil.
06-07-2019 11:07 AM - edited 06-07-2019 11:08 AM
06-13-2019 03:03 PM
08-30-2019 05:17 AM
I actually went with a different route. I used Vivado and just compiled the example design for the board. Then, linked it to the build. I loaded that one and it works. It's basically allowing user to control gpios