UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
846 Views
Registered: ‎05-31-2018

PL load error via fpgautil on zcu111, zynqmp_clk_divider_set_rate() set divider failed

Hi all,

I am trying to load the PL portion of my design through FPGA manager, which for the moment is a test design with only a few gpios and a ddr4 memory ip core. My project compiles and I've generated the bitstream, and am able to do some standard LED blinks through a baremetal driver through the SDK.

Now I wanted to load the PS onto a linux system and try using FPGA manager to load the PL afterwords. I followed the main steps, petalinux-create -> petalinux-config with my .hdf file and fpga manager selected, as well as petalinux-build and petalinux-package.

After this, I put my BOOT.bin and image.ub on an SD card and am able to boot my file system and kernel.

Now, when I want to load the PL, I do an scp of the .bit.bin and the .dtbo files that petalinux generated for my project, namely, the files in 

/project_dir/build/tmp/sysroots-components/zcu111_zynqmp/fpga-manager-util/lib/firmware/base/design.bit.bin, and base.dtbo

Now that I have it on my machine, I try a fpgautil -b design_1_wrapper.bit.bin -o base.dtbo , and get the following message through the console:

root@xilinx-zcu111-2018_3:~/temp_files# fpgautil -b design_1_wrapper.bit.bin -o base.dtbo
[ 427.020618] fpga_manager fpga0: writing design_1_wrapper.bit.bin to Xilinx ZynqMP FPGA Manag
er
[ 427.275452] zynqmp_clk_divider_set_rate() set divider failed for pl0_ref_div1, ret = -13
Time taken to load DTBO is 266.000000 Milli Seconds
DTBO loaded through zynqMP FPGA manager successfully

I receive this message regardless of trying another projects hardware files, also created through the petalinux interface (I'm using petalinux 2018.3). 

Does anyone have any idea as to why this is? I can also provide my hardware design if needed, but it is not much more than a ZynqMP+, ddr4, a bram and a few gpios.

0 Kudos
8 Replies
Moderator
Moderator
831 Views
Registered: ‎09-12-2007

Re: PL load error via fpgautil on zcu111, zynqmp_clk_divider_set_rate() set divider failed

This flow is covered here:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841645/Solution+Zynq+PL+Programming+With+FPGA+Manager

If your use case is to not have the PL bitstream in the BOOT.BIN (ie if booting over tftp for example), then you can do the following:

Creating Image in Petalinux 2018.3:

  • petalinux-create -t project -s <path to BSP>.bsp
  • cd <plnx project>
  • petalinux-config

dtbo.png

  • petalinux-config -c kernel
    • config as shown here
  • petalinux-build
  • cd images/linux
  • petalinux-package --boot --u-boot

I have a helper script that you can use (attached here)

Creating BIN, and DTO:

 

Launch XSCT, and source the attached helper script. Run the commands below:

  • generate_dts <path to HDF>.hdf
  • bit2bin <path to HDF>.hdf

fpga_man_files.png

Testing on Hardware:

Place the BOOT.BIN, image.ub, design_1_wrapper.bit.bin, pl.dtbo onto an SD card and boot:

sd_files.png

Use the commands on the wiki to test:

console.png

Contributor
Contributor
822 Views
Registered: ‎05-31-2018

Re: PL load error via fpgautil on zcu111, zynqmp_clk_divider_set_rate() set divider failed

Hi Stephen,

Thank you for your response, however, I noticed you also received the zynqmp_clk_divider_set_rate() set divider failed for pl0_ref_div1, ret = -13 error as I did.

This seems to affect how the clock works for certain IPs such as the GPIO.

 

0 Kudos
Contributor
Contributor
795 Views
Registered: ‎05-31-2018

Re: PL load error via fpgautil on zcu111, zynqmp_clk_divider_set_rate() set divider failed

Also, do you get this set divider failed for pl0_ref_div1 message even when using FPGA_Manager (meaning the fpgautil command) ?
0 Kudos
765 Views
Registered: ‎03-12-2019

Re: PL load error via fpgautil on zcu111, zynqmp_clk_divider_set_rate() set divider failed

Did you end up figuring out the reason for this?

I also ran into the same thing using fpgautil.

0 Kudos
Contributor
Contributor
715 Views
Registered: ‎05-31-2018

Re: PL load error via fpgautil on zcu111, zynqmp_clk_divider_set_rate() set divider failed

Nope still didn't find the reason
0 Kudos
699 Views
Registered: ‎03-12-2019

Re: PL load error via fpgautil on zcu111, zynqmp_clk_divider_set_rate() set divider failed

@az23 

I tried the latest release 2019.1. The issue seems to go away now. I use zcu102 but I suggest you give it a try.

I guess there was a regression in the previous version.

0 Kudos
Contributor
Contributor
631 Views
Registered: ‎05-31-2018

Re: PL load error via fpgautil on zcu111, zynqmp_clk_divider_set_rate() set divider failed

Did FPGA Manager work without any issues for you for petalinux 2019.1? Trying a simple design I get the following message:

/lib/firmware/base# fpgautil -b design_1_wrapper.bit.bin -o base.dtbo
[ 51.852643] fpga_manager fpga0: writing design_1_wrapper.bit.bin to Xilinx ZynqMP FPGA Manager
[ 51.927141] fpga_manager fpga0: Error while writing image data to FPGA
[ 51.940380] fpga_region region0: failed to load FPGA image
[ 51.945881] OF: overlay: overlay changeset pre-apply notifier error -22, target: /fpga-full
[ 51.954226] OF: overlay: overlay changeset pre-apply notify error -22
[ 51.960671] create_overlay: Failed to create overlay (err=-22)
0 Kudos
334 Views
Registered: ‎03-12-2019

Re: PL load error via fpgautil on zcu111, zynqmp_clk_divider_set_rate() set divider failed

I actually went with a different route. I used Vivado and just compiled the example design for the board. Then, linked it to the build. I loaded that one and it works. It's basically allowing user to control gpios

0 Kudos