UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor jcompadr
Visitor
284 Views
Registered: ‎01-15-2019

PL shared interrupt not been activated

Hi, I am trying to activate a shared interrupt in the processing system. It will be activated by a signal created in my custom IP, which will be active for some time.

I am able to use a private interrupt (Core0_nFIQ), the interrupt handler function is executed correctly when my custom signal is activated. However I am interested in using a shared interrupt, but when I conect my signal to this shared interrupt, after configuring it in the SDK, it does not seem to work.

When I try to use the shared interrupt, in addition to the configuration for the private one, I have configured "XScuGic_SetPriorityTriggerType" and "XScuGic_InterruptMaptoCpu" when using the shared interrupt. I have also changed the interrupt "ID to XPS_FPGA0_INT_ID"

 

Here is my Block Design:

Capture.PNG

 

And my C code to configure the interrupt:

 

#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
#include "myip_bram_pl_controller.h"
#include "xil_io.h"
#include "xparameters.h"
#include "Xscugic.h"
#include "Xil_exception.h"

#define FPGA_INT XPS_FPGA15_INT_ID//XPS_IRQ_INT_ID//
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID

static void FPGAIntrHandler(void *CallBackRef);
static void SetupInterruptSystem(XScuGic *GicInstancePtr, u32 *FPGAPtr, u16 FPGAIntrId);

static XScuGic Intc; //GIC
static u32 FPGA;


void * addr = (void *) XPAR_MYIP_BRAM_PL_CONTROL_0_S00_AXI_BASEADDR;

int main()
{
u32 * destination;

init_platform();

printf("Configuring interrupt\n\r");

destination = (u32 *)XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR;

MYIP_BRAM_PL_CONTROLLER_mWriteReg(XPAR_MYIP_BRAM_PL_CONTROL_0_S00_AXI_BASEADDR,MYIP_BRAM_PL_CONTROLLER_S00_AXI_SLV_REG0_OFFSET,0); //enable

SetupInterruptSystem(&Intc,&FPGA,FPGA_INT);

while(1){}

cleanup_platform();
return 0;
}

 

static void SetupInterruptSystem(XScuGic *GicInstancePtr, u32 *FPGAPtr, u16 FPGAIntrId)
{
int Status;

XScuGic_Config *IntcConfig; //GIC config

//initialise the GIC
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
XScuGic_CfgInitialize(GicInstancePtr, IntcConfig,
IntcConfig->CpuBaseAddress);


//Perform a self-test to ensure that the hardware was built correctly. ADDED
Status = XScuGic_SelfTest(GicInstancePtr);
if (Status != XST_SUCCESS) {
print("GIC SelfTest Failed\n\r");
return XST_FAILURE;
}

Xil_ExceptionInit();

//connect to the hardware
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
GicInstancePtr);

//set up the timer interrupt
XScuGic_Connect(GicInstancePtr, FPGAIntrId,
(Xil_ExceptionHandler)FPGAIntrHandler,
(void *)FPGAPtr);

//ADDED for shared interrupt
XScuGic_SetPriorityTriggerType(GicInstancePtr, FPGAIntrId, 8, 0b11);
XScuGic_InterruptMaptoCpu(GicInstancePtr, 0, FPGAIntrId);

//enable the interrupt for the Timer at GIC
XScuGic_Enable(GicInstancePtr, FPGAIntrId);

// Enable interrupts in the Processor.
Xil_ExceptionEnableMask(XIL_EXCEPTION_ALL);//Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ); //Xil_ExceptionEnable();

printf("Interrupt Set Up\n\r");
}

static void FPGAIntrHandler(void *CallBackRef)
{

printf("FPGA Interrupt Event\n\r");
}

Tags (3)
0 Kudos