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Visitor jetlyrajat
Visitor
7,648 Views
Registered: ‎05-09-2010

PLB Bus Error / PPC440 Interrupt Handling

Hello Everyone,

 

Problem : PPC440 Machine Check Interrupt handling in case of Data Read PLB error.

 

I have been trying to write an interrupt handler for the PPC440 in case of a PLB read error.

But the PPC handles a PLB read error as an imprecise machine check interrupt. i.e. the PC is set to the address of the next instruction to be executed instead of the load/store instruction that actually caused the interrupt / error. This leads to the cache being loaded with incorrect data.

 

For the load/store instruction to be completed correctly the PC has to be moved backwards to point to the load/store instruction that caused the interrupt. (I think so ... Please correct me if I am wrong here.) This can be done by decrementing the PC field in the program stack frame, in the interrupt handler routine.

 

But, the problem is that the amount of decrement that needs to be done on the PC, differs from one case to the other. It depends upon the C code written and compiler optimization etc .

 

Could you please provide me with some pointers, as to how I could get around this problem.

 

Thanks & Regards

 

- Rajat

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6 Replies
Adventurer
Adventurer
7,621 Views
Registered: ‎01-04-2008

Re: PLB Bus Error / PPC440 Interrupt Handling

I believe the PPC440 has several "exception syndrome registers" that contain the program counter value of the faulting instruction.  The exception handler can then look at these registers (ESSR0, SRR0) to make a decision as to how to handle the exception, as well as which PC value to return control to.

 

-Jason

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Visitor jetlyrajat
Visitor
7,608 Views
Registered: ‎05-09-2010

Re: PLB Bus Error / PPC440 Interrupt Handling

Hi Jason

 

Thanks for your reply. I have been using these registers and they are only partially helpful. Let me illustrate my problem in some detail.

 

I have a ML510 board where I use the PPC440 (Virtex-5) to read some data from DDR2- DIMM0. I use the MPMC core (PLB interface) as the memory controller. I use the Standalone BSP for my project, which contains the xvectors.S file for interrupt handling. The routines in this file are responsible for saving the machine state on the stack, calling the registered interrupt handler and restoring the machine state from the stack.

Following is what I wish to do-

1.) Trigger PLB Read Data Error when the PPC tries to access a particular range of addresses in the DDR (a load/store instruction)

2.) Do some further processing in the interrupt handler routine

3.) Then, re-trigger the load/store instruction that caused the interrupt in the first place.

 

Now, a Read Data Error on the PLB triggers a Machine Check Interrupt in the PPC. The registers affected by the Machine Check interrupt are -

MCSRR0 (holds the PC, i.e. the next instruction to be executed after interrupt handling has been completed and not the instruction that caused the interrupt)

MCSRR1 (holds the MSR),

MCSR (indicates the cause of the interrupt – PLB Read Error in this particular case).

 

Here is a line of code and its disassembly :

 

k = DIMM_0[99];

 

ffff06e4:           3d 20 ff ff         lis     r9,-1

ffff06e8:           81 29 25 9c     lwz     r9,9628(r9)

ffff06ec:           39 29 01 8c     addi    r9,r9,396

ffff06f0:            80 09 00 00     lwz     r0,0(r9)

ffff06f4:            3d 20 ff ff         lis     r9,-1

ffff06f8:            90 09 25 a0     stw     r0,9632(r9)

 

Here, the instruction that triggers the interrupt is

            ffff06f0:            80 09 00 00     lwz     r0,0(r9)

and MCSRR0 (PC), at the point of interrupt handling points to  

            ffff06f8:            90 09 25 a0     stw     r0,9632(r9)

Now to successfully re-trigger the load instruction at address ffff06f8, I have to decrement the PC by 20 to point to address            ffff06e4.

 

Here is another example line of code and its disassembly :

 

xil_printf("k = %x, i = %x\r\n", DIMM_0[99], DIMM_0[99]);

 

ffff06e4:           3d 20 ff ff         lis     r9,-1

ffff06e8:           81 29 25 7c     lwz     r9,9596(r9)

ffff06ec:           39 29 01 8c     addi    r9,r9,396

ffff06f0:            81 69 00 00     lwz     r11,0(r9)

ffff06f4:            3d 20 ff ff         lis     r9,-1

ffff06f8:            81 29 25 7c     lwz     r9,9596(r9)

ffff06fc:            39 29 01 8c     addi    r9,r9,396

ffff0700:           80 09 00 00     lwz     r0,0(r9)

ffff0704:           3d 20 ff ff         lis     r9,-1

ffff0708:           38 69 20 b0     addi    r3,r9,8368

ffff070c:           7d 64 5b 78     mr      r4,r11

ffff0710:           7c 05 03 78     mr      r5,r0

ffff0714:           48 00 0a 49     bl      ffff115c <xil_printf>

 

Here, the instruction that triggers the interrupt is

            ffff06f0:            81 69 00 00     lwz     r11,0(r9)

and MCSRR0 (PC), at the point of interrupt handling points to  

            ffff0700:           80 09 00 00     lwz     r0,0(r9)

Now to successfully re-trigger the load instruction at address ffff06f0, I have to decrement the PC by 28 to point to address            ffff06e4.

 

So here is the crux of my problem:

How do I decrement the PC in a way that I have the correct data and program flow in all cases. As the amount of decrement changes from 20 to 28 in the two cases, and there could be more such possible cases.

 

Thanks & Regards

- Rajat

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Xilinx Employee
Xilinx Employee
7,600 Views
Registered: ‎04-23-2008

Re: PLB Bus Error / PPC440 Interrupt Handling

A machine check is not like a Program Exception.  Depending on what type of error has occurred, you may not have *any* of the usual debug info available.  The short version is that there simple isn't any way around this.

 

Perhaps have a peek at XAPP1117.

 

-Brian

 

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Visitor jetlyrajat
Visitor
7,595 Views
Registered: ‎05-09-2010

Re: PLB Bus Error / PPC440 Interrupt Handling

Hi Brian

 

Thanks for your reply. I had feared this.

 

But a question in general - Is there a way to trigger a synchronous precise interrupt (behavior similar to a program exception) from a source external to the PPC?

 

As in my particular case, I need a load/store instruction under some conditions, to trigger an exception condition with the memory controller being a possible source. For ex. Could something be done in software, at the OS level so that a Data Storage exception is triggered ?

 

Thanks & Regards

- Rajat

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Highlighted
Adventurer
Adventurer
7,386 Views
Registered: ‎01-04-2008

Re: PLB Bus Error / PPC440 Interrupt Handling

I'm not exactly sure of what you are trying to implement, but wouldn't the MMU and virtual addressing help you out?

 

Then, instead of a machine check exception (which isn't necessarily recoverable) you would be dealing with memory faults (which are recoverable).

 

-Jason

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Visitor esiturbo
Visitor
6,289 Views
Registered: ‎11-04-2011

Re: PLB Bus Error / PPC440 Interrupt Handling

Hi

 

Can somebody help me how can I write into PC?

 

Ehsan

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