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Visitor gconstantine
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2,570 Views
Registered: ‎07-12-2013

PLB-based peripheral read/write to DDR

I am creating a peripheral that will read/write to the DDR memory through the PLB bus.

Adhering to the specifications in the PLB_MASTER_BURST ipif user manual, I assert the signals exactly as described. I am not able to do a single-beat read, or a burst read from the DDR (mpmc) slave on the bus. After configuring the signals for a request, SOF and EOF go LOW (without the bus asserting Bus2IP_Cmd_Ack).

 

At first I thought there was a problem with my plb_master implementation, so I created a plb_slave ipif using the peripheral wizard, and was able to read from it normally.

Does the mpmc on the plb bus fully comply with the specifications? Is this a bug?

 

I have been tackling this for almost a week. Has anybody had any success with read/write from a peripheral to the DDR (not using a microblaze core?)

 

I have tried 14.1 ,14.4,14.6 versions of the ISE. I am using a XUPV5 virtex5 board.

Thanks for any help! 

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Visitor gconstantine
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2,556 Views
Registered: ‎07-12-2013

Re: PLB-based peripheral read/write to DDR

EDIT: After viewing the MPMC mpd file, it seems that the default definition doesn't allow for bursts on a plb port. 

Does anybody know what the correct procedure would be to enable slave burst access on a plb port of the MPMC?

 

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