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Visitor
Visitor
4,633 Views
Registered: ‎06-19-2008

PORT CLKOUT1

I have MicroBlaze and for user peripheral I need other clk than sys_clk_s. I want to use clock_generator_0 and in this one

PORT CLKOUT0 = sys_clk_s
PORT CLKOUT1 = clock_generator_0_CLKOUT1

However, I do not know how can I get clock_generator_0_CLKOUT1 in periferie. Could you help me, please.

Kral

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Xilinx Employee
Xilinx Employee
4,620 Views
Registered: ‎08-02-2007

Re: PORT CLKOUT1

Hello,

 

When you configure the clock generator, you can connect the CLKOUT1 signal to the ports that exist in the drop down list.

 

Or you can directly  modify the MHS

 

PORT CLKOUT1 = clock of the peripheral.

 

Rgds 

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Visitor
Visitor
4,609 Views
Registered: ‎06-19-2008

Re: PORT CLKOUT1

Could you help me in more detail, please?
Already after the configuration of the clock generator the following line appeared in file MHS

PORT CLKOUT1 = clk_div1

In periphery I have

--USER ports added here
   clk_div1      : in   STD_LOGIC;

Nevertheless, I still result in the error

Dangling pins on
  block: clock_generator_0........
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Visitor
Visitor
4,607 Views
Registered: ‎06-19-2008

Re: PORT CLKOUT1

I think that it is also necessary to modify file my_periphery.MPD and in MHS file instance my_periphery, however, I do not know how to do this.
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