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Contributor
Contributor
2,165 Views
Registered: ‎11-18-2016

PS - PL communication

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Hi sir,

I have connected different peripherals(DDC(1553-B) chip, Digital inputs, Digital outputs,UART) at PL side. but i want to control it by using PS. For that i have written AXI slave VHDL program.Master AXI Reading and writing results are displaying an PS-UART on host PC.

When AXI master reading --->  The address asserting by master AXI is fine.

                                           --->  The Data asserting by Slave(VHDL logic at PL side) is delaying 500 ns. (Reading DDC chip and corresponding data asserting on AXI slave)

* may be processor does not waiting that time , not getting result at HOST PC.

 

Then i have taken "AXI lite - APB" bus bridge to communicate PL but vivado not assigning the address to AXI-APB bridge. but when i am making it to external it is assigning the address. After assigning the address  i am making my APB logic in PL.but no results have observing in host PC.

 

* Please suggest the best way to communicate PL and PS.

*What is the maximum Processor( AXI master) wait time while reading from AXI slave?

 

Regards

Kasarla Ganesh

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1 Solution

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Xilinx Employee
Xilinx Employee
2,525 Views
Registered: ‎02-01-2008

Re: PS - PL communication

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Keep in mind that you are using Xil_In32 and Xil_Out32 which are exercising 32bit accesses. So your print format should be 0x%08x, temp should be unsigned int or better yet, u32, and your offset should increment by 4 due to the 32bit accesses.

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4 Replies
Mentor watari
Mentor
2,158 Views
Registered: ‎06-16-2013

Re: PS - PL communication

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Hi @ganeshpatel

 

I don't have any answers. But I suggest to do simulation with ZYNQ VIP by xsim to clarify the route cause and to estimate a wait time.

Would you try it ?

 

https://www.xilinx.com/support/documentation/ip_documentation/processing_system7_vip/v1_0/ds940-zynq-vip.pdf

 

Best regards,

 

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Contributor
Contributor
2,122 Views
Registered: ‎11-18-2016

Re: PS - PL communication

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Hi sir,

thanks for replying me. I tried what you suggested, but not in XSIM, on Hardware tried.finally i concluded its not delaying problem.

its writing problem of AXI master. i follwed below code SDK.

 

 

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my base address is 0X8000_0000. If i write base adress as  0X8000_0000 and offset as 0x0. then i am able to writing it and also
able to reading it. But if increase my offset address then writing and reading was not performing.

 

 * if it is only writing and reading of a base address.

  

1.Example iteration code :

i= 0;
     while (1) {
      set_custom_ip_register(0x80000000, i, 0xa5a5); //set_custom_ip_register(base address, offset address, Data);
      xil_printf(".\r\n");
      temp5=get_custom_ip_register(0x80000000, 0x1); //get_custom_ip_register(base address, offset address);
      printf("Register 3 = 0x%02X\n\r", temp5);
*/
        xil_printf("2\r\n");
     }

conclusion : writing and reading success full.

 

 

2.Example iteration code :



    /* receive and process packets */
     while (1) {

         set_custom_ip_register(0x80000000, 0, 0xa5a5); //set_custom_ip_register(base address, offset address, Data);

        temp3=get_custom_ip_register(0x80000000, 0);    //get_custom_ip_register(base address, offset address);
        printf("Register 3 = 0x%02X\n\r", temp3);

//---------up to here reading and writing fine---------------------

//------------if i increase offset address then its not performing
         set_custom_ip_register(0x80000000, 0x2, 0xc5c5);
        temp4=set_custom_ip_register(0x80000000, 0x4, 0xe5e5);*/
         printf("Register 3 = 0x%02X\n\r", temp4);
         xil_printf("2\r\n");
     }

conclusion : writing and reading address failed at offset address >1.

 

regards

Kasarla Ganesh

 

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Xilinx Employee
Xilinx Employee
2,526 Views
Registered: ‎02-01-2008

Re: PS - PL communication

Jump to solution

Keep in mind that you are using Xil_In32 and Xil_Out32 which are exercising 32bit accesses. So your print format should be 0x%08x, temp should be unsigned int or better yet, u32, and your offset should increment by 4 due to the 32bit accesses.

View solution in original post

Contributor
Contributor
2,005 Views
Registered: ‎11-18-2016

Re: PS - PL communication

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Hi sir,

Thanks  for your reply, i got the solution.

Thanks & Regards

Ganesh Kasarla

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