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Observer umer.sabeen
Observer
8,563 Views
Registered: ‎11-26-2015

PS-PL voltage level shifter

Hello

I am new in vivado,

I want to transfer (transmit/receive) data through SPI, following is my design.

Screenshot from 2016-01-08 11:40:52.png

As in the documents said , spi0_ss or spi1_ss should be connected to the VCC. i did that  and the second thing is hoe can i enable LVL_SHFTR_EN , because in the ug898 it is clearly written "You must enable the PL level shifters using LVL_SHFTR_EN before PL logic communication can occur.

thanks in advance

 

 

3 Replies
Xilinx Employee
Xilinx Employee
8,285 Views
Registered: ‎08-01-2012

Re: PS-PL voltage level shifter

umer.sabeen mentioned that --As in the documents said , spi0_ss or spi1_ss should be connected to the VCC.

Please specify which document are you referring? Also clearly explain what is your exact requirement and what are the problems?

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949 Views
Registered: ‎07-31-2018

Re: PS-PL voltage level shifter

@umamahe hi there, I am pretty sure he/she reffers to the Zynq-7000 TRM document. In chapter 17 SPI Controller, under figure 17-8 it is mentioned, that the PS-PL voltage level shifters must be turned on.

 

I would like to open this topic again for discussion, because I am facing the same problem (how to activate the PS-PL level shifters) and because of this the SPI communication is not working properly.

 

Controlling the level shifter would be relative easy in my opinion in a bare-metal application, because the relevant header files and register manipulation functions/macros are already available. However, I am working with an embedded Linux environment and I DO NOT UNDERSTAND how to integrate the relevant BSPs into my environment...

I am facing SPI communication problems and I am pretty sure it has a lot to do (or almos everything) with the level shifters.

I am getting randomly "spi transfer timeout" errors from Linux, although my MISO has data. Moverover, when this error occurs, stays permanently until a complete power off and on. Simple Linux "restart" does not suffice to solve the problem. It seems like a HW relevant problem, and probably voltage levels relevant...

 

I have attached an oscilloscope screenshot from an SPI communication. The PL contains an IP-Core, which is working and tested... so it is not the reason of the problem.

 

Questions:

-how to integrate the BSPs into a Linux environment?

-how to set the required voltage level shifters?

 

Thanks in advance for every help!

spi_problem_zynq.png
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Scholar ronnywebers
Scholar
576 Views
Registered: ‎10-10-2014

Re: PS-PL voltage level shifter

As far as I'm aware, the enabling of the level shifters happens in the FSBL, more precisely in the function 'FsblHandoff' in main.c

  • In case you use a FSBL to boot your system, ps7_init.c/h will enable the shift registers for you (it's a huge file, but you can search for 'shift' in that file, and you should see the correct values set there.
  • In case you use JTAG to download your bitstream/code (hence there's no FSBL) -> an equivalent tcl script 'ps7_init.tcl' enables the level shifters (search for 'PS_LVL_SHFTR_EN' in that file).

All these files (ps7_init.c/h and ps7_init.tcl) are extracted by SDK from the .hdf file that is generated during a Vivado 'export hardware'. So I assume Vivado should set the right flags in case you enable EMIO, and you don't need to worry about this.

 

 

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