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Visitor ewalls
Visitor
155 Views
Registered: ‎10-16-2018

Preload an AXI Stream FIFO for Simulation

I was hoping to find help with a simulation.  I have a piece of custom IP:

  1. The IP connects to a stream FIFO and expects to read 5 x 32bit words from the FIFO to configure itself. 
  2. Once the config FIFO has been read the IP expects to find data in a second streaming FIFO.  It reads the data in, one word at a time, does "stuff" and sends it out on a third streaming FIFO.

I would like to load both input FIFOs with some data so that when I start the simulation the IP block is able to be verified.  I can force the TReady signal on the output FIFO so I’m not worried about that part.

I've simulated the IP without the FIFOs but I'd like to verify it works with them and with multiple data elements without having to write a complex testbench.

Any advice will be greatly appreciated.  Thank you.

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Xilinx Employee
Xilinx Employee
79 Views
Registered: ‎10-04-2016

Re: Preload an AXI Stream FIFO for Simulation

Hi @ewalls ,

I don't think there is a back door way to pre-load the contents of the FIFO.

Have you looked at the AXI4-Stream Verification IP? You could use it to push data into the FIFO from the S_AXI interface. It might simplify the amount of work you need to do to get the necessary commands into your FIFO.

https://www.xilinx.com/products/intellectual-property/axi-stream-vip.html

Regards,

Deanna

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