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Observer yfortin
Observer
1,091 Views
Registered: ‎05-25-2015

Problem making a AXI port external

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Hi,

 

  I have a design targeting Zynq-7030 that is working. Most of the logic is currently contained inside a single Block Design. But now there is one 3rd-party IP inside that Block design that I need to take out and isolate into its own separate Block Design. Then I want to connect the two Block Designs together in top level using VHDL wrappers. The architecture is the same after the modification, it's just a rearrangement of the IP files for better modularity. My problem is that the 3rd-party IP is not responding anymore after I split the Block design.

 

  There are two AXI ports on that 3rd-party IP; one master and one slave.The slave port appears to be working fine, since I am reading/writing to it. The master port I believe is not working after the modification. The master port is AXI4 protocol. It connects to S_AXI_HP0 of the Zynq Processing System and is used for the IP to fetch its firmware from Zynq memory. That firmware is stored at offset 0x0F000000 of the Zynq PS, while the address range of the master AXI4 port is 0x00000000 to 0x0FFFFFFF (256MB) and is defined in both Block Designs.

 

  I believe that the master port is not working and the IP cannot execute its firmware, hence the absence of response. The master port (through AXI Interconnect 2.1 block) and the S_AXI_HP0 ports have both been made external to allow for top-level connection in VHDL. However it seems like the characteristics of those ports is not identical to what I was getting when the IP was confined inside the same Block Design as the Zynq PS.

 

  - The ARID, AWID, BID, RID signals do not exist on the Zynq PS side, but they do exist on the IP side. I had to leave them unconnected or forced to zero on top level.

  - The AXI4 interface has 32 bits (4G) on the Zynq PS side, but only 31 bit (2G) on the IP side.

 

  I suspect that the communication is not working correctly on the Master AXI4 ports due to these discrepancies. It's just a theory at this point but I'll try to prove it using ILA debug core.

 

  Is there a way to get (or force) identical parameters on both sides of that AXI4 port?

 

  Thank you,

  Yannick.

 

 

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Observer yfortin
Observer
1,066 Views
Registered: ‎05-25-2015

Re: Problem making a AXI port external

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Hi Deanna,

 

  Thank you very much for your response, and for taking the time to try it out on Vivado 2018.1.

 

  My issue is now resolved; I have realized that by clicking on the AXI port I get access to "External Interface Properties" windows where the "Properties" tab allows me to change some parameters. Among them was the ID_WIDTH parameter which was set to 0 by default. After setting to 2 and recompiling, the design is functional again.

 

  Thank you very much for your help!

  Yannick.

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Xilinx Employee
Xilinx Employee
1,001 Views
Registered: ‎10-04-2016

Re: Problem making a AXI port external

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Hi @yfortin,

I'm not sure why your transactions aren't crossing over into the Zynq block diagram. Those ILA traces will really help to figure out where the signal gets lost.

 

The IP side needs to drive all 32 bits of address, even if it just ties off bit 31 to 1'b0. 

 

I created a block diagram for the Zynq-7000 in 2018.1 and made the S_AXI_HP0 ports external. When I create the wrapper for the block diagram, I see S_AXI_HP0_0_arid, _awid, _bid, _rid and _wid in the port list of the wrapper. All five ports are six bits wide. 

 

In the block diagram, if I highlight the external interface flag and look at its properties, I see ID_WIDTH set to 6. I'm not sure why you are seeing something different. These signals should be present at the port.

 

Please keep in mind that the AXI interfaces on the Zynq-7000 are AXI3, so you'll need to add a protocol converter to manage the burst lengths and WID signals. Do you have this in your Zynq BD?

 

Regards,

 

Deanna

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Observer yfortin
Observer
1,067 Views
Registered: ‎05-25-2015

Re: Problem making a AXI port external

Jump to solution

Hi Deanna,

 

  Thank you very much for your response, and for taking the time to try it out on Vivado 2018.1.

 

  My issue is now resolved; I have realized that by clicking on the AXI port I get access to "External Interface Properties" windows where the "Properties" tab allows me to change some parameters. Among them was the ID_WIDTH parameter which was set to 0 by default. After setting to 2 and recompiling, the design is functional again.

 

  Thank you very much for your help!

  Yannick.

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