UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor cesarcf
Visitor
389 Views
Registered: ‎06-13-2018

Problem with AXI-Stream in a DDR-DMA-Ethernet dataflow

Hello,

My idea is about sending data from a DDR Memory through the AXI 1G/2.5G Ethernet Subsytem IP using Stream transfers with a DMA block. The FPGA is connected to a PC (via Ethernet cable) in which Wireshark is running in promiscuous mode.

The problem is that Wireshark does not received anything from the FPGA. Debugging the system I found that the AXI-Stream link between Ethernet and DMA blocks does not move any data. By means of an ILA connected to this link I watch that TKEEP and TVALID signals are asserted but the other ones (TREADY, TDATA, TLAST) are not. 

The block diagram is shown below:

 


Anotación 2019-02-01 124650.jpg 

I did not find any design example with this configuration and I think that my problem is more related to software configuration than hardware, or maybe I am wrong and the block diagram is not correct.

I am using the following code:


#include "xil_printf.h"
#include "xparameters.h"
#include "xaxiethernet.h"
#include "xaxidma.h"

#define DDR4_BASEADDR (XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR)

#define SIZE (64)

XAxiEthernet MAC_GigE;
XAxiDma DMA_GigE;

int main(){

/***** Variables declaration *****/
int Status;
int ddr[SIZE];
u8 MAC_addr[6] = {0x00, 0x0A, 0x35, 0x33, 0x33, 0x33};

/* IPs configuration */
XAxiEthernet_Config *MacCfgPtr;
XAxiDma_Config *DmaConfig;

/* Get the configuration of AxiEthernet hardware */
MacCfgPtr = XAxiEthernet_LookupConfig(XPAR_AXIETHERNET_0_DEVICE_ID);
/* Get the configuration of DMA */
DmaConfig = XAxiDma_LookupConfig(XPAR_AXI_ETHERNET_0_DMA_DEVICE_ID);

/*
* Initialize AXIDMA engine. AXIDMA engine must be initialized before
* AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
* reset, and since AXIDMA reset line is connected to AxiEthernet, this
* would ensure a reset of AxiEthernet.
*/
Status = XAxiDma_CfgInitialize(&DMA_GigE, DmaConfig);
if(Status != XST_SUCCESS) {
xil_printf("Error initializing DMA\r\n");
return XST_FAILURE;
}

/* Disable interrupts, we use polling mode */
XAxiDma_IntrDisable(&DMA_GigE, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DEVICE_TO_DMA);
XAxiDma_IntrDisable(&DMA_GigE, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DMA_TO_DEVICE);

/* Initialize AxiEthernet hardware */
Status = XAxiEthernet_CfgInitialize(&MAC_GigE, MacCfgPtr, MacCfgPtr->BaseAddress);
if (Status != XST_SUCCESS) {
xil_printf("Error in initialize");
return XST_FAILURE;
}

XAxiEthernet_SetMacAddress(&MAC_GigE, MAC_addr);
XAxiEthernet_SetOptions(&MAC_GigE, XAE_TRANSMITTER_ENABLE_OPTION);
XAxiEthernet_Start(&MAC_GigE);

// Checking functions
xil_printf("SGMII: %d\n\r", XAxiEthernet_GetPhysicalInterface(&MAC_GigE) == XAE_PHY_TYPE_SGMII);
xil_printf("Is started?: %d\n\r", XAxiEthernet_IsStarted(&MAC_GigE));
xil_printf("IsDma: %d\n\r", XAxiEthernet_IsDma(&MAC_GigE));
xil_printf("IsMcDma: %d\n\r", XAxiEthernet_IsMcDma(&MAC_GigE));
xil_printf("DMA has Scatter-Gather: %d\n\r", XAxiDma_HasSg(&DMA_GigE));

xil_printf("\n\n\rLaunching program...\n\r");

xil_printf("Before: ");
for(int i = 0; i < SIZE; i++)
xil_printf("%d ", ddr[i]);

*ddr = DDR4_BASEADDR;
for(int i = 0; i < SIZE; i++)
ddr[i] = i+1;

xil_printf("\n\rAfter: ");
for(int i = 0; i < SIZE; i++)
xil_printf("%d ", ddr[i]);
xil_printf("\n\r");

xil_printf("%d\n\r", XAxiDma_SimpleTransfer(&DMA_GigE, (UINTPTR)ddr, SIZE, XAXIDMA_DMA_TO_DEVICE));

return 0;}


Another problem comes up after running this application: the program gets stuck within "XAxiEthernet_CfgInitialize", while executing "XAxiEthernet_Reset" function. If I comment this instruction, the program finishes correctly: XAxiDma_SimpleTransfer returns 0, but it does not send anything, indeed. 

Maybe I am forgetting something during the configuration, but I wrote the code following the examples provided by Xilinx. Do you have any idea this design is not working? 

Thank you in advance!!

Extra info:

KCU105 (KU040)
Vivado 2018.1

0 Kudos