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Adventurer
Adventurer
199 Views
Registered: ‎04-11-2019

Problem with the IIC IP clock setting

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For unclear reason can't modify in Vivado 2017.4 the  SCL Clock from 100KHz to 400Khz. AXI clock in IP setting is 100MHz.

In the simulation I see  the IIC IP input AXI clock frequency is 100MHz but SCL Clock still as default 100KHz.

Can you explain?

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1 Solution

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Xilinx Employee
Xilinx Employee
119 Views
Registered: ‎04-09-2019

Re: Problem with the IIC IP clock setting

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Hi,

Kindly confirm are you using PS or PL IIC.

Regards,

Venu

View solution in original post

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2 Replies
178 Views
Registered: ‎06-21-2017

Re: Problem with the IIC IP clock setting

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You didn't tell us which device you are using or whether this is from the PL or PS side of a Zynq.  If it is the PS side of a Zynq, this is fromthe Tech Ref Guide for the Ultrascale+

The I2C controllers can function as a master or a slave in a multi-master design. They can
operate over a clock frequency range up to 400 kb/s.

This is probably limited by the drive strength of the pins. 

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Xilinx Employee
Xilinx Employee
120 Views
Registered: ‎04-09-2019

Re: Problem with the IIC IP clock setting

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Hi,

Kindly confirm are you using PS or PL IIC.

Regards,

Venu

View solution in original post

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