12-13-2019 05:56 AM
For unclear reason can't modify in Vivado 2017.4 the SCL Clock from 100KHz to 400Khz. AXI clock in IP setting is 100MHz.
In the simulation I see the IIC IP input AXI clock frequency is 100MHz but SCL Clock still as default 100KHz.
Can you explain?
12-13-2019 07:39 AM
You didn't tell us which device you are using or whether this is from the PL or PS side of a Zynq. If it is the PS side of a Zynq, this is fromthe Tech Ref Guide for the Ultrascale+
The I2C controllers can function as a master or a slave in a multi-master design. They can
operate over a clock frequency range up to 400 kb/s.
This is probably limited by the drive strength of the pins.