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Newbie yokohara
Newbie
403 Views
Registered: ‎01-14-2019

QSPI Controller

Hi
I have a question which I hope you could answer.
I am creating a program that reads (Command: QOR (0x6B)) Flash on the ZC 706 Board from the QSPI Controller.
But I can not read the correct value.
When checking the waveform, the QSPI Controller outputs an extra 6 Cycle between Command + Address and Data Read Cycle.
We anticipate that the QSPI Controller is outputting Dummy Cycle.
QSPI Controller outputs Dummy Clock?
And, please tell me how to control it.

thanks.

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3 Replies
Xilinx Employee
Xilinx Employee
327 Views
Registered: ‎09-01-2014

Re: QSPI Controller

You would need to add dummy bytes.
here is an example I modified FSBL to use EB command for reading, in this case, dummy byte of 5 is set

#define LQSPI_CR_FAST_QUAD_IO_READ 0x000000EB
#define LQSPI_CR_5_DUMMY_BYTE 0x500
#define DUAL_STACK_CONFIG_QUAD_IO_READ ( XQSPIPS_LQSPI_CR_LINEAR_MASK | \
XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
LQSPI_CR_5_DUMMY_BYTE | \
LQSPI_CR_FAST_QUAD_IO_READ )
XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_STACK_CONFIG_QUAD_IO_READ);
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Newbie yokohara
Newbie
315 Views
Registered: ‎01-14-2019

Re: QSPI Controller

Thank you for your early response.

However, this problem was not solved.

This is a problem when unnecessary dummy bytes of 3 bytes are output when reading data of flash memory via QSPI.

I set the dummy byte of the LQSPI_CR register to 0, but I can not understand why the dummy byte is output at the time of reading.

Please tell me the register setting so as not to output dummy byte when reading.

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Xilinx Employee
Xilinx Employee
290 Views
Registered: ‎09-01-2014

Re: QSPI Controller

Have you tried QSPI example design on ZC706? It's no problem to read as 6B command.
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/qspips/examples/xqspips_flash_polled_example.c
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