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Visitor draeman
Visitor
2,085 Views
Registered: ‎04-20-2016

QSPI dual parallel - list of supported flash commands

I have a board with a Zynq-7000 and two Micron flash chips connected via QSPI in dual parallel mode. According to TRM v1.11 page 355-356, the QSPI controller snoops the flash command for each transfer and manages the two chips based on the command ID. For example-- read/write commands stripe each byte of data bitwise across the chips, sector erase command sends a copy of the command to each chip, and read status register command will return the value from the lower bus but will bitwise-or bit 7 from the upper bus.

 

I'm developing a custom driver and cannot find a comprehensive list of behaviors for each command that the QSPI controller is aware of, and how it might handle commands that it's unaware of. In those cases, does it dispatch the command to both chips or just the lower bus? Is there an AR or other resource with this information?  I'd like to make sure I understand the behavior if I use less common commands such as a deep-sleep command, use of lock registers or NVM configuration registers, etc.  And I'd like to understand how reading other status registers (i.e. flag status register) combine chip responses across the bitfields.

 

Thank you.

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3 Replies
Scholar ericv
Scholar
2,060 Views
Registered: ‎04-13-2015

Re: QSPI dual parallel - list of supported flash commands

@draeman

 

You can get the list of recognized commands in the register section of the TRM:

Look into the LQSPI_CFG register; in the V1.11 TRM, it's around page 1536.

For the reports / data / register read etc, bottom p.355 / top p.356

The Quad-SPI controller does a read from the two Quad-SPI devices and ORs (or operation) both device’s status information before writing the status data in the RXFIFO.

 

You get an ORed value of both chips reports.

 

Regards

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Scholar ericv
Scholar
2,040 Views
Registered: ‎04-13-2015

Re: QSPI dual parallel - list of supported flash commands

@draeman

 

As you are using the QSPI I/F with 2 chips, I assume throughput is important.

The controller can only insert dummy bytes, not dummy cycles.

At their max clock rates, all devices require dummy cycles and most times it's not an exact multiple of 8 bit xfers.

You can easily overcome this and reach the max clock rate by manually doing the dummy cycle insertion in your driver: shifting / dropping selected read bits.

Plus, although the Zynq' ARMs are little endian, configuring the controller I/F to be big endian makes the shifting much easier.

 

Regards

 

 

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Scholar pratham
Scholar
2,024 Views
Registered: ‎06-05-2013

Re: QSPI dual parallel - list of supported flash commands

@draeman No there is no such list exists to best of my knowledge.

-Pratham

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