02-28-2018 03:43 PM
I'm trying to use a Microblaze to write configuration words to an Analog Devices part; it uses a standard 24-bit SPI transaction.
Is there an example of this using the AXI QuadSpi?
08-21-2018 01:04 PM - edited 08-21-2018 01:46 PM
I need to talk to an AMC7812. It uses SPI transfers based on 24 bit words. The biggest problem is that the device requires the chip select line to be toggled after every 24 bit word. To "emulate" this, I would have to chose 8 bit word width and do lots of small 3 byte transfers. That would cause lots and lots of interrupts.
Also, attached to the same SPI bus are other devices which use regular 8bit words, where the chip select line stays low continuously.
Transaction width could really just be a counter in the IP core that tells when the chip select line needs to be triggered. Then, that counter could also be changed at runtime.
Anyhow, proper support for 24 word width would allow me to use the 256 byte FIFO and read all ADC channels with a single SPI transaction, for example, with minimal effort for the CPU.
08-21-2018 02:08 PM
Talked to some folks, and the answer is apparently to use the Manual Slave Select mode of the core...you deliberately push SS low first by a write to the SPI Slave Select Register (0x70) with the bit set for the correct device. You then successively write the Data Transmit Register for 3 bytes, then you can put the SPI Slave Select back to 1.
I'm doing polled mode so that's not dealing with interrupts. Fortunately I don't have do push this out too often/fast.
08-21-2018 03:09 PM
Yes, you set SS low, then send 3 byte, then set SS high when you get the interrupt that the 3 byte have been sent. But now you have to wait for a few ns before you set SS low again and you send the next 3 bytes.
The problem is doing that interrupt based. I'm struggling to implement the delay between setting SS hight and setting SS low again.
A timer could be used, but I'd have to reserve a timer for especially that purpose.
Also, if SPI is running at 10MHz, having an interrupt every 3 bytes would be an interrupt every 2400ns. That just sounds very very crazy.
What about the SPI in the PS. Does it support anything other than 8bit words at all?