Question about VHDL and Verilog in building custom core.

[kakashi0]

I am working on XUPV2P board.

I don't understand why all of the tutorial documents of Xilinx are introduced in VHDL but all of the example for Virtex  II Pro are written by Verilog?

I tried to build the template core by Verilog although I don't know much about Verilog, but I didn't see any relation between a template core generate by wizard with the example go with the XUPV2P >_<. It's really hard to learn from these examples. I would highly appreciate if some one can send me a project working with Video written by VHDL? Or any project builds a PLB custom core which has interrupt function.

Thank you so much for your time.

[kakashi0]

One more question:

When I want to build the core by verilog, I can only build the user_core by verilog, not the whole peripheral which include the IPIF module and user_core. The peripheral module is built by VHDL. But in all of the example, all of them are built by Verilog?

I get lost =.=

[jeffrey.johnson]

For the VGA design example, you can download one from this page. Its called "256 MB Single Rank DDR Memory with VGA controller".

http://www.eecg.toronto.edu/~jarvin/

For the PLB custom core with interrupts, check the Aurora and Timer examples on this website. It is a site with online tutorials and example designs for the XUP Virtex-II Pro board. All the examples are in VHDL and they have step instructions with screen shots and source code.

http://www.fpgadeveloper.com

Good luck.

Message Edited by jeffrey.johnson on 01-18-2009 05:32 PM

[kakashi0]

Is it true that the cores in example of Xilinx were built manually? I ask this question, because when I try to build it with Verilog option, the top IP is still built in VHDL. While all of these IPs are built with verilog.

In case we build a core manually, how should we make the system recorgnizes these cores?

Thank you so much.

Message Edited by kakashi0 on 04-08-2008 09:42 PM

[jeffrey.johnson]

I imagine the cores in the Xilinx examples were written manually.

If you manually build a core, you should place it in the "pcores" folder. When the design is complete, you can select from the menu "Project->Rescan User Repositories" and it will be placed in the "IP Catalog". You can then create an instance of the core in your project.

[golson]

Hi,

I see the same thing about almost all of the wrappers, ect are VHDL files even when you have selected Verilog output.  However, the implementation files that are output by BSB are

the system.v and system_stub.v files.  Along with several *.ngc files for the subcomponents.  The XST synthesis tool will use the verilog files and the NGC files to create a

place and routed design.

I took the system.v, system_stub.v and the NGC files and placed in a XST project and the files will compile to a FPGA programming file with just these files.

[kakashi0]

Golson,

Could you please tell me where the system.v and system_stub.v file locate?

What I have after generate a verilog core is a user_logic.v file and the main core in vhdl.

Thank you,

Message Edited by kakashi0 on 04-14-2008 09:53 PM

[golson]

In my design I found them in the HDL directory.

C:\BSB_PRACTICE\APR14_08_VERILOG\hdl

[centaur19]

Hi Kakashi,

Yes, you are right. When you create a custom peripheral and choose Verilog, only the user logic will be in Verilog. The IPIF will be in VHDL. The user_logic is the file you would use to write your custom logic. This is primarily because most of our IPs are in VHDL.

Gary,

I think you are talking about the implementation wrappers. You can choose the top level wrapper to be either Verilog or VHDL. While the individual core wrappers will be in the language they were written, you get to choose the language for system/system_stub. So you would have system.v or system.vhd depending on your selection. This is the file you would use to instantiate your EDK system if it were a sub-module. Again the default is VHDL.