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Adventurer
Adventurer
4,441 Views
Registered: ‎04-07-2011

Regarding AXI 4 Master Burst mode

Hi

I want to design an AXI4 Master which does a read from say 256 DDR locations and fills it into a FIFO of some specified depth. The read operation is in a specified address range after which the master needs to repeat the read from the base address again (as per my design). So, I could infer that I would require a wrapping burst mode.
Please correct me if I am wrong.
I need to design this custom AXI4 master using a state machine. Assuming that it will be a wrapping burst mode, where one burst is equal to 16 transfers and one transfer is equal to 16 bytes, and the FIFO data width is equal to 4 bytes per locations, one complete burst would fill up 64 burst locations.
Now, for the wrap burst mode, I have the following queries.
1.    From what I could gather as per the protocol, the read address needs to be given only for the 1st byte of the burst transfer along with the other control signals - ARLEN, ARSIZE, ARBURST, ARPROT, ARLOCK, and ARCACHE.
I have assumed the following values for my design.
ARLEN         = 16 (“1111”)
ARSIZE         = 4 (“100”)
ARBURST     = “00”
ARCACHE     = “0011”
ARLOCK         = ‘0’
ARPROT         = “000”

Please correct me if I am wrong in these assumptions.

2.    For this wrap burst mode, do I need to assign the address along with the necessary control information, only in the beginning of the burst? If yes, then how would my Master know when should I assign the address again?
By this I mean, say one burst is successfully completed and I need to repeat the process for the next burst again, starting from the base address. In this case will the AXI4 interconnect infer the base address? Since, I would have selected wrapping burst mode or, I would have to again send the address and the necessary control information for the 2nd burst?

3.    Within a data beat / data transfer, is there any gap between 2 successive RVALID or it is continuously asserted for 1 complete ARSIZE?

4.    Between any 2 successive transfers in a data burst, is there any gap or the RREADY signal in my state machine is continuously asserted till the end of the burst?

5.    How would my AXI4 master know that one complete burst transaction is over? Is it that I can keep a counter which increments on every RLAST signal received from the AXI4 slave (in this case AXI4 interconnect)?

Request to please reply to my queries asap.

 

akanksha112

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