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Explorer
Explorer
2,649 Views
Registered: ‎07-17-2014

[SOLVED] AXI partial transfers over greater bus width

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Hey all,

Question on AXI transfers (using AXI Stream bus) into a DMA Receiver (the DMA module)

I have a 64bit Data width, but have a situation where I'm sending data that's only 48 bits worth (the upper bytes can be discarded.)

I haven't tried it yet -- but considered the possibility of manipulating the appropriate TKEEP/TSTRB (I need to go look at the protocol doc again.)

My goal is to have a single transfer cycle that's only 6 bytes wide (out of 8) which only increases the systems RCV'd byte count by 6 (and appropriately throws away those top 2 bytes).

Any thoughts from anyone? (before I go chase down an idea that won't work?)

Thanks,

 -Ben

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Explorer
Explorer
4,650 Views
Registered: ‎07-17-2014

Re: AXI partial transfers over greater bus width

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As it turns out, the best solution was to simply set the BMP "start of image" offset past the padding of extra null bytes that are inserted into the data stream due to the 64bit bus width caused by the BMP header.

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Xilinx Employee
Xilinx Employee
2,627 Views
Registered: ‎08-02-2011

Re: AXI partial transfers over greater bus width

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Hi Ben,

I would use an AXI Stream Data Width Converter IP in front of the DMA. It will efficiently merge multiple beats of the 48 bit interface into 64 bit data width for use with the DMA.
www.xilinx.com
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Explorer
Explorer
2,618 Views
Registered: ‎07-17-2014

Re: AXI partial transfers over greater bus width

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Hi -- thanks for the reply. I don't think I explained the problem clearly enough.

normally this data stream is all 64bits wide. (I'm pushing a BMP header through it and then the image data.)

but the BMP header specification is only 14bytes.

So that's 1 transfer of 8 bytes (64 bits) and then another transfer of 6 bytes (48bits) over the same bus.

Everything else down the road is 64bit aligned. It's just this one transfer that doesn't need a full 64bits.

Reading the AXI spec, it looks like I can lower TKEEP for those 16bits (2 TKEEP lines) and that gets tossed from the data stream.

I'm going to try it out and see if that works.

 

 -Ben

 

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Explorer
Explorer
4,651 Views
Registered: ‎07-17-2014

Re: AXI partial transfers over greater bus width

Jump to solution

As it turns out, the best solution was to simply set the BMP "start of image" offset past the padding of extra null bytes that are inserted into the data stream due to the 64bit bus width caused by the BMP header.

0 Kudos