11-25-2016 09:13 AM
Hello. I'm working in a SPI testbed with the following settings:
XC72045 MASTER SPI (SPI is on PS)
XC72020 SLAVE SPI (SPI is on PL build with VIVADO Intelletual Properties AXI_QUAD_SPI)
I'm trying to trasfer a file with a lenght of 512 bytes
Master and Slave are linked with a track of about 10cm
With this configuration i'm just able to receive 335 B on slave and 256 B on master. The remaining bytes are received dirty
On master SPI FIFO LENGHT TX-RX is 128
On slave SPI FIFO LENGHT TX-RX is 256
The only thing who pilots the transmission interrupt is fifo_queue_len=0 (no threshold)
I've used XILINX functions and default settings
Could you please help me to understand me what i'm doing wrong. My target is to be able, with this configuration, to transfer a file long about 15MB
Thanks in advance
11-25-2016 12:41 PM
11-27-2016 07:50 AM
11-29-2016 12:25 AM
We have tried different configurations varying fifo tx-rx depth , threshlod no-threshold, pre-scaler clock but we didn't obtaing good results.
I agree with you that seems to be a clock dis-alignment between master and slave but unfortunately i'm not able to use an oscilloscope because there's not enough space on the plane for the probes.
Could you provide me please a C source example code, including SPI initialization, for PS MASTER AND PL SLAVE so i can check it and use for my testbed.
I'm confident that your code has been tested for this kind of scenario.
Thanks in advance
11-29-2016 08:12 AM
This morning I've also tried to use xilinx functions example imported from SDK 2015.1.
For AXI_QUAD_SPI (with 2 differente tests) i've tried with
For SPI_PS i've used
3. xspips_(flash)_intr_example substituting target flash with spi_slave (PL)
Unfortunately i've obtained the same results of my custom functions (perhaps obtained from xilinx example modifying parameters such as fifo depth , prescaler...).
I've used xspi_slave_polled_example to verify that the problem wasn't on interrupt management.
How I could further investigate this problem.
11-30-2016 07:08 AM
Regarding your question about FIFO I've observed that FIFO TX of AXI QUAD SPI has:
12-06-2018 10:59 AM
We're having the same issue with the Axi Quad SPI IP. Every now and then we get a data abort when writing to the SPI Data Transmit Register. It seems to happen only when the SDK debugger is being used. Any ideas of what is going on or how to debug?