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Visitor darkiaspis
Visitor
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Registered: ‎10-27-2014

SPI does not receive correctly depending on supplied clock frequency

Hi mates.

I was wondering about a reasonable explanation about an error of my SPI configuration onto a Xilinx Zynq 7010 (a zybo board, actually).

 

I prepared a PS environment with the SPI0 configured as a master (SS_IN tied to 1) and a SPI1 configured as slave, both of them routed through the emio port.

My aim is to connect two zybos communicating through two SPI channels, hence the master of a board is directly connected to the slave of the other one, and vice versa.

The SPI clock reference, by default, is configured to be 1000/6 MHz = 166.666 MHz and, since it is routed throught the EMIO (implying a maximum frequency of 25MHz), the SPI prescaler must be greater than or equal to 8 (maximum available frequency is about 20.8MHz). I configured also the clock polarity to be 1.

 

In this configuration I am not able to receive correctly the bytes I'm transmitting, even though probing the signals SCLK, MISO and MOSI I got a perfect signalling.

 

Hence, I decided to try other different clock configuration. I tried to configure the PLL divider to 5, getting 200 MHz of SPI clock reference, and I got nothing correct even with lower prescaler value (8, 16, 32, 64... really weird). In this case, the signalling is really weired:

https://imgur.com/a/UEBDqsb (yellow: clock, cyan: mosi, magenta: miso)

 

I gave up to go for so much faster speeds, then I decided to go with a lower PLL divider (7), getting a SPI clock reference of 142 MHz, but guess what happened... nothing. Bytes I'm receiving are wrong.

 

Such behavior is not random: each time I execute my SPI transferring I got the same wrong bytes.

 

As a desperate, I started to not trust my oscilloscope and I tried to loop-back MISO and MOSI. Surprisingly with a PLL divider 6 and prescaler 6 (10 MHz of SPI clock) i got someting correct.

 

Please, can you help me to clarify if I can go someway to an arbitrary close-to-25MHZ frequency getting two Zynq-7010 communicating through SPI? I would be really grateful as I am not able to retrieve other infos.

 

 

P.s. from the Zynq-7000 TRM, on SPI chapter (pag 555) the guide suggests to configure the PLL divider to 10 and getting 100 MHz of SPI clock reference. This is not possible since the SPI clock reference must be faster than the Clock_1x of the PS system. Actually I am not able to get such a configuration. If I correctly comprehended, to configure the SPI clock reference to 100 MHz, do I have to sacrifice my system performance degradating the Clock_1x?

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