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Adventurer
Adventurer
4,835 Views
Registered: ‎03-03-2010

SSTL135 Incompatible on zynq: PAR error

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I have a zynq design which uses DIFF_SSTL135 pin pairs in banks 34 and 35 on the zynq 010clg225-1 device.

 

I get an error during PAR that this standard is compatible, however Page 98 of the 7 Series SelectIO resources guide says that this standard should be available for both bank types. 

 

Here's my error:

 

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1556.191 ; gain = 0.000 ; free physical = 5003 ; free virtual = 12459
ERROR: [Place 30-372] Bank.34 has terminals with incompatible standards:
SioStd: DIFF_SSTL135 VCCO = 1.35 Termination: 0  TermDir:  Out  Bank: 34 Placed LVDS 
ERROR: [Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|                                                                     IO Placement : Bank Stats                                                                           |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins  | Terms |                               Standards                                |                IDelayCtrls               |  VREF  |  VCCO  |   VR   | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|  0 |     0 |     0 |                                                                        |                                          |        |        |        |     |
| 34 |    46 |    36 | DIFF_SSTL135(36)                                                       |                                          |        |  +1.35 |    YES |     |
| 35 |     8 |     8 | DIFF_SSTL135(8)                                                        |                                          |        |  +1.35 |    YES |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|    |    54 |    44 |                                                                        |                                          |        |        |        |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+

IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId |             Terminal | Standard        | Site                 | Pin                  | Attributes           |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 34     | clkin1_clk_p         | DIFF_SSTL135    | IOB_X0Y24            | N11                  |                      |
|        | clkin1_clk_n         | DIFF_SSTL135    | IOB_X0Y23            | N12                  |                      |
|        | clkout_clk_p         | DIFF_SSTL135    | IOB_X0Y28            | K11                  |                      |
|        | clkout_clk_n         | DIFF_SSTL135    | IOB_X0Y27            | K12                  |                      |
|        | datain1_p[0]         | DIFF_SSTL135    | IOB_X0Y16            | R12                  |                      |
|        | datain1_n[0]         | DIFF_SSTL135    | IOB_X0Y15            | R13                  |                      |
|        | datain1_p[1]         | DIFF_SSTL135    | IOB_X0Y10            | R7                   |                      |
|        | datain1_n[1]         | DIFF_SSTL135    | IOB_X0Y9             | R8                   |                      |
|        | datain1_p[2]         | DIFF_SSTL135    | IOB_X0Y20            | P15                  |                      |
|        | datain1_n[2]         | DIFF_SSTL135    | IOB_X0Y19            | R15                  |                      |
|        | datain1_p[3]         | DIFF_SSTL135    | IOB_X0Y18            | P11                  |                      |
|        | datain1_n[3]         | DIFF_SSTL135    | IOB_X0Y17            | R11                  |                      |
|        | datain1_p[4]         | DIFF_SSTL135    | IOB_X0Y4             | P8                   |                      |
|        | datain1_n[4]         | DIFF_SSTL135    | IOB_X0Y3             | P9                   |                      |
|        | datain1_p[5]         | DIFF_SSTL135    | IOB_X0Y8             | M10                  |                      |
|        | datain1_n[5]         | DIFF_SSTL135    | IOB_X0Y7             | M11                  |                      |
|        | datain1_p[6]         | DIFF_SSTL135    | IOB_X0Y2             | P10                  |                      |
|        | datain1_n[6]         | DIFF_SSTL135    | IOB_X0Y1             | R10                  |                      |
|        | datain1_p[7]         | DIFF_SSTL135    | IOB_X0Y34            | L15                  |                      |
|        | datain1_n[7]         | DIFF_SSTL135    | IOB_X0Y33            | M15                  |                      |
|        | datain1_p[8]         | DIFF_SSTL135    | IOB_X0Y36            | N13                  |                      |
|        | datain1_n[8]         | DIFF_SSTL135    | IOB_X0Y35            | N14                  |                      |
|        | datain1_p[9]         | DIFF_SSTL135    | IOB_X0Y14            | P13                  |                      |
|        | datain1_n[9]         | DIFF_SSTL135    | IOB_X0Y13            | P14                  |                      |
|        | dataout1_p[1]        | DIFF_SSTL135    | IOB_X0Y32            | L14                  |                      |
|        | dataout1_n[1]        | DIFF_SSTL135    | IOB_X0Y31            | M14                  |                      |
|        | dataout1_p[4]        | DIFF_SSTL135    | IOB_X0Y30            | K13                  |                      |
|        | dataout1_n[4]        | DIFF_SSTL135    | IOB_X0Y29            | L13                  |                      |
|        | dataout1_p[5]        | DIFF_SSTL135    | IOB_X0Y48            | G11                  |                      |
|        | dataout1_n[5]        | DIFF_SSTL135    | IOB_X0Y47            | H12                  |                      |
|        | dataout1_p[6]        | DIFF_SSTL135    | IOB_X0Y46            | G12                  |                      |
|        | dataout1_n[6]        | DIFF_SSTL135    | IOB_X0Y45            | H13                  |                      |
|        | dataout1_p[7]        | DIFF_SSTL135    | IOB_X0Y42            | J15                  |                      |
|        | dataout1_n[7]        | DIFF_SSTL135    | IOB_X0Y41            | K15                  |                      |
|        | dataout1_p[8]        | DIFF_SSTL135    | IOB_X0Y40            | J13                  |                      |
|        | dataout1_n[8]        | DIFF_SSTL135    | IOB_X0Y39            | J14                  |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 35     | dataout1_p[0]        | DIFF_SSTL135    | IOB_X0Y98            | F12                  |                      |
|        | dataout1_n[0]        | DIFF_SSTL135    | IOB_X0Y97            | E13                  |                      |
|        | dataout1_p[2]        | DIFF_SSTL135    | IOB_X0Y90            | G15                  |                      |
|        | dataout1_n[2]        | DIFF_SSTL135    | IOB_X0Y89            | F15                  |                      |
|        | dataout1_p[3]        | DIFF_SSTL135    | IOB_X0Y96            | E11                  |                      |
|        | dataout1_n[3]        | DIFF_SSTL135    | IOB_X0Y95            | E12                  |                      |
|        | dataout1_p[9]        | DIFF_SSTL135    | IOB_X0Y94            | F13                  |                      |
|        | dataout1_n[9]        | DIFF_SSTL135    | IOB_X0Y93            | F14                  |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+

INFO: [Timing 38-35] Done setting XDC timing constraints.

...
ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. Ending Placer Task | Checksum: 110cdee12 Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:04 . Memory (MB): peak = 1594.199 ; gain = 38.008 ; free physical = 5002 ; free virtual = 12458 INFO: [Common 17-83] Releasing license: Implementation 36 Infos, 22 Warnings, 0 Critical Warnings and 4 Errors encountered. place_design failed ERROR: [Common 17-69] Command failed: Placer could not place all instances

 

Is there any documentation mentioning that this bank is not compatible with this standard? Or am I doing something else wrong?

 

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Xilinx Employee
Xilinx Employee
8,293 Views
Registered: ‎07-11-2011

Re: SSTL135 Incompatible on zynq: PAR error

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Hi,

 

The error says that Bank 34 has incompatible IOstandards which means you have location constarints with more than one IOstandard.

 

Please refer Rules for Combining I/O Standards in the Same Bank section of UG471 and cross check if LVDS and SSTL are compatible IOstandards

 

 

Hope this helps

-Vanitha

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3 Replies
Xilinx Employee
Xilinx Employee
8,294 Views
Registered: ‎07-11-2011

Re: SSTL135 Incompatible on zynq: PAR error

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Hi,

 

The error says that Bank 34 has incompatible IOstandards which means you have location constarints with more than one IOstandard.

 

Please refer Rules for Combining I/O Standards in the Same Bank section of UG471 and cross check if LVDS and SSTL are compatible IOstandards

 

 

Hope this helps

-Vanitha

---------------------------------------------------------------------------------------------
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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

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Community Manager
Community Manager
4,808 Views
Registered: ‎07-23-2012

Re: SSTL135 Incompatible on zynq: PAR error

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Can you please share the .dcp file to investigate on this issue?
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Adventurer
Adventurer
4,798 Views
Registered: ‎03-03-2010

Re: SSTL135 Incompatible on zynq: PAR error

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I've figured out the problem. 

 

There was an erroneus external pin that I fogot to delete. It was autoallocated to a pin in that bank using the default LVDS25. 

 

The LVDS wasn't incompatible with SSTL135, so that caused the error.

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