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Visitor vttmw93
Registered: ‎09-21-2018

SWDT Clock In PCB/package skew to Reset Out

I am using the xtp427 checklist to verify our Zynq MPSoC schematic design.  The PS-MIO interface section specifies that the PCB and package skew between SWDT 'Clock In' and 'Reset Out' should be within +/- 100 ps.  Since we are using an internal clock rather than the external MIO 'Clock In' pin for our SWDT clock, I assume this requirement can be ignored?  More generally, I don't understand this requirement.  How can there be a "skew" relationship between an input signal and an output signal?  If the 'Reset Out' changed state following a particular 'Clock In' edge, wouldn't this be a "propagation delay" rather than a "skew"?

Any help is greatly appreciated.

Thanks, Ted  

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