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Observer
Observer
3,126 Views
Registered: ‎11-14-2016

SWDT Output Selection

I have a quick question about the Zynq SWDT peripheral. Here's a snippet from the TRM:

 

Capture.PNG

According to this, there is no way to assert an MIO pin on reset if the SWDT uses the internal clock (WDT_CLK_SEL == 0). This seems strange to me and doesn't really line up with the block diagram from the TRM:

 

Capture.PNG

 

Is this an error in the TRM? Or can I really not assert an MIO pin on reset unless I use an external SWDT clock source?

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Visitor
Visitor
1,692 Views
Registered: ‎08-29-2017

Re: SWDT Output Selection

Hi,

 

I have exactly the same interrogation of the SWDT description found in the Zynq TRM:

Does external clock is required as input to assert MIO pin on watchdog timeout?

Do you have any updates to provide?

 

I try to verify by myself but unfortunately, whatever my SWDT registers configuration is (and sclr.WDT_CLK_SEL + sclr.MIO_PIN_XX), I'm not able to have an MIO pin assertion (MIO 15 in my case) when watchdog timeout is trigged.

 

Does anyone already use successfully this feature and/or have a sample code to provide with the suitable configuration?

 

Thank you in advance for your help or comment.

 

Regards,

 

Tom

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Moderator
Moderator
1,646 Views
Registered: ‎07-31-2012

Re: SWDT Output Selection

Hi @meigva,

 

in currect version of TRM we have corrected the section 8.4.7 Reset Output Option for SWDT as below:

The following code shows how the AP SoC selects the reset output pin for SWDT:
if slcr.MIO_PIN_15[7:0] is 01100000, use MIO pin 15
else if slcr.MIO_PIN_27[7:0] is 01100000, use MIO pin 27
else if slcr.MIO_PIN_39[7:0] is 01100000, use MIO pin 39
else if slcr.MIO_PIN_51[7:0] is 01100000, use MIO pin 51
else if slcr.MIO_PIN_53[7:0] is 01100000, use MIO pin 53
else use EMIOWDTRSTO

The watchdog reset is sent to the PS reset subsystem to cause a non-POR reset, see section
26.3 Reset Effects. The reset output to the MIO pin or EMIOWDTRSTO is active High.

As note mentions, it says to generate a signal pulse for the PS_POR_B and other board resets, route the EMIOWDTRSTO signal from the SWDT through the PL and to a pin that can be externally latched to generate a valid reset pulse. Alternatively, use an external watchdog timer device that is managed by PS software via a GPIO output pin. The PS_POR_B reset pulse width requirements are defined in the data sheet.

 

How are you writing into these registers? Is it thru any application or registerwr/rd ?

 

 


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Contributor
Contributor
1,400 Views
Registered: ‎09-24-2016

Re: SWDT Output Selection

I can confirm outputting SWDT reset out on an external MIO pin works, also with the SWDT working from the internal clock. (The MIO pin configuration does not allow to set this combo, but it works if you program the pin-mux yourself.)

 

Question:

 

Can the SWDT generate a reset only on the MIO output pin, without generating an internal (CPU) reset?

 

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Moderator
Moderator
1,354 Views
Registered: ‎07-31-2012

Re: SWDT Output Selection

Hi @likewise,

 

SWDT reset complete subsystem and wont be restricted to just pin.

 

Regards

Praveen


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Contributor
Contributor
1,340 Views
Registered: ‎09-24-2016

Re: SWDT Output Selection

Hi @pvenugo,

thank you for clarifying. I have another post on “SWDT documentation”. Could you please answer that, as it is related?

Thank you,

Leon
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