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Adventurer
Adventurer
5,645 Views
Registered: ‎04-11-2012

Second EmacLite ethernet port not working

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I have a board with two Ethernet ports and PHYs.  I've instantiated two axi_ethernetlite cores in EDK 14.3.  In SDK, I've generated the default lwIP echo server demo application.

 

If I set PLATFORM_EMAC_BASEADDR to XPAR_AXI_ETHERNETLITE_0_BASEADDR, and connect a network cable to the first port, then it works as expected -- I can ping the board from another PC and connect to the echo server and send/receive data.

 

If I then change to XPAR_AXI_ETHERNETLITE_1_BASEADDR and connect the cable to the second port, I cannot ping or connect to the board.  (But I do get link and activity lights.)

 

The problem is not the hardware; I tried reversing the pin assignments in the UCF file (swapping the physical ports) and still only the first address (which is now the second physical port) works as expected.

 

The two cores are configured identically except for base address and MDIO (but I tried swapping MDIO and it had no effect):

 

BEGIN axi_ethernetlite
 PARAMETER INSTANCE = axi_ethernetlite_0
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_BASEADDR = 0x44000000
 PARAMETER C_HIGHADDR = 0x4400FFFF
 PARAMETER C_S_AXI_PROTOCOL = AXI4LITE
 PARAMETER C_INCLUDE_INTERNAL_LOOPBACK = 1
 PARAMETER C_S_AXI_ID_WIDTH = 1
 PARAMETER C_RX_PING_PONG = 1
 PARAMETER C_TX_PING_PONG = 1
 PARAMETER C_INCLUDE_MDIO = 1
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHzPLL0
 PORT PHY_tx_clk = enet_phy1_mii_tx_clk_pin
 PORT PHY_rx_clk = enet_phy1_mii_rx_clk_pin
 PORT PHY_crs = enet_phy1_mii_crs_pin
 PORT PHY_dv = enet_phy1_mii_rx_dv_pin
 PORT PHY_rx_data = enet_phy1_mii_rx_data_pin
 PORT PHY_col = enet_phy1_mii_col_pin
 PORT PHY_rx_er = enet_phy1_mii_rx_err_pin
 PORT PHY_tx_en = axi_ethernetlite_0_PHY_tx_en
 PORT PHY_rst_n = axi_ethernetlite_0_PHY_rst_n
 PORT PHY_tx_data = axi_ethernetlite_0_PHY_tx_data
 PORT IP2INTC_Irpt = axi_ethernetlite_0_IP2INTC_Irpt
 PORT PHY_MDC = axi_ethernetlite_0_PHY_MDC
 PORT PHY_MDIO = axi_ethernetlite_0_PHY_MDIO
END

BEGIN axi_ethernetlite
 PARAMETER INSTANCE = axi_ethernetlite_1
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_BASEADDR = 0x45000000
 PARAMETER C_HIGHADDR = 0x4500FFFF
 PARAMETER C_S_AXI_PROTOCOL = AXI4LITE
 PARAMETER C_INCLUDE_MDIO = 0
 PARAMETER C_INCLUDE_INTERNAL_LOOPBACK = 1
 PARAMETER C_S_AXI_ID_WIDTH = 1
 PARAMETER C_RX_PING_PONG = 1
 PARAMETER C_TX_PING_PONG = 1
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_100_0000MHzPLL0
 PORT PHY_tx_clk = enet_phy2_mii_tx_clk_pin
 PORT PHY_rx_clk = enet_phy2_mii_rx_clk_pin
 PORT PHY_crs = enet_phy2_mii_crs_pin
 PORT PHY_dv = enet_phy2_mii_rx_dv_pin
 PORT PHY_rx_data = enet_phy2_mii_rx_data_pin
 PORT PHY_col = enet_phy2_mii_col_pin
 PORT PHY_rx_er = enet_phy2_mii_rx_err_pin
 PORT PHY_rst_n = axi_ethernetlite_1_PHY_rst_n
 PORT PHY_tx_en = axi_ethernetlite_1_PHY_tx_en
 PORT PHY_tx_data = axi_ethernetlite_1_PHY_tx_data
 PORT IP2INTC_Irpt = axi_ethernetlite_1_IP2INTC_Irpt
END

 Any ideas what could be causing this, or what I can try to diagnose it further?

1 Solution

Accepted Solutions
Adventurer
Adventurer
7,231 Views
Registered: ‎04-11-2012

Re: Second EmacLite ethernet port not working

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Turns out the problem was just that the echo demo application enables XPAR_INTC_0_EMACLITE_0_VEC_ID directly and independently from the PLATFORM_EMAC_BASEADDR specified.  (I'm not really sure why the lwIP interface layer doesn't enable the interrupt itself -- it does when using xilkernel, but not standalone.)

 

Enabling the interrupt for the second port make it work as expected, although there are a few more traps for the unwary in getting both ports to work at once.  (And in dealing with a shared MDIO bus.)

View solution in original post

4 Replies
Adventurer
Adventurer
7,232 Views
Registered: ‎04-11-2012

Re: Second EmacLite ethernet port not working

Jump to solution

Turns out the problem was just that the echo demo application enables XPAR_INTC_0_EMACLITE_0_VEC_ID directly and independently from the PLATFORM_EMAC_BASEADDR specified.  (I'm not really sure why the lwIP interface layer doesn't enable the interrupt itself -- it does when using xilkernel, but not standalone.)

 

Enabling the interrupt for the second port make it work as expected, although there are a few more traps for the unwary in getting both ports to work at once.  (And in dealing with a shared MDIO bus.)

View solution in original post

Adventurer
Adventurer
5,596 Views
Registered: ‎04-11-2012

Re: Second EmacLite ethernet port not working

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I'm still getting a slightly odd behaviour, but I'm not sure if this is a bug or expected.

 

I've assigned unique MAC and IP addresses to each adapter.  If I bring either of them up (netif_set_up) by itself, then both pings and echo connections work perfectly.

 

If I bring both of them up at the same time (even when only one of them is actually physically connected to a network) then pings work ok but attempts to connect to echo fail (the TCP ACK is never received by the remote PC).

 

The echo server works again if I ensure the two IP addresses are not in the same subnet.

 

Is this normal or not?

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Adventurer
Adventurer
5,589 Views
Registered: ‎04-11-2012

Re: Second EmacLite ethernet port not working

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Ok, never mind.  I know that having two NICs on the same subnet is a problem even for PCs, I was just hoping that it would be able to simply route traffic out the same port that it came in on.  I'll just change the way that I'm trying to use the ports so that this isn't a problem any more.

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659 Views
Registered: ‎07-11-2018

Re: Second EmacLite ethernet port not working

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how to connect MDIO pins(52,53) in PS side for two ethernets in processor (PS) side send a connection

diagram in hardware for designing. We have requirement for two ethernets from PS side

regards

mahendra

design engineer

hyderabad

india

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